74ALVC244PW,112 NXP Semiconductors, 74ALVC244PW,112 Datasheet - Page 2

• Manufacturer Part Number: 74ALVC244PW,112
• Description: IC BUFF/DVR TRI-ST DUAL 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCr

Specifications of 74ALVC244PW,112

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 4
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Logic Family: ALVC
• Logical Function: Buffer/Line Driver
• Number Of Elements: 2
• Number Of Channels: 8
• Number Of Inputs: 8
• Number Of Outputs: 8
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: TSSOP
• Output Type: 3-State
• Polarity: Non-Inverting
• Propagation Delay Time: 6.9ns
• High Level Output Current: -24mA
• Low Level Output Current: 24mA
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.65V
• Quiescent Current: 20uA
• Technology: CMOS
• Pin Count: 20
• Mounting: Surface Mount
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Number Of Channels Per Chip: 8
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 8 / 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVC244PW; 74ALVC244PW; 935269725112

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 Sep 08
t
C
C
PHL
SYMBOL
Wide supply voltage range from 1.65 to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V)
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
I
PD
Octal buffer/line driver; 3-state
P
f
f
C
V
N = total load switching outputs;
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay nAn to nYn
input capacitance
power dissipation capacitance per buffer
2
V
CC
= 25 C.
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
PARAMETER
L
CC
.
V
CC
2
f
o
) where:
V
V
V
V
V
2
CC
CC
CC
CC
CC
DESCRIPTION
The 74ALVC244 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC244 is an octal non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
= 1.8 V; C
= 2.5 V; C
= 2.7 V; C
= 3.3 V; C
= 3.3 V; notes 1 and 2
D
in W).
CONDITIONS
L
L
L
L
= 30 pF; R
= 30 pF; R
= 50 pF; R
= 50 pF; R
L
L
L
L
= 1 k
= 500
= 500
= 500
Product specification
2.7
2.0
2.3
2.2
3.5
20
TYPICAL
74ALVC244
ns
ns
ns
ns
pF
pF
UNIT