74ACT541SCX Fairchild Semiconductor, 74ACT541SCX Datasheet - Page 7

• Manufacturer Part Number: 74ACT541SCX
• Description: IC BUFF/DVR TRI-ST 8BIT 20SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74ACTr

Specifications of 74ACT541SCX

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: 74ACT
• Number Of Channels Per Chip: Octal
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Input Bias Current (max): 4 uA
• Low Level Output Current: 24 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 3
• Output Type: 3-State
• Propagation Delay Time: 7 ns @ 5 V
• Logical Function: Buffer/Line Driver
• Number Of Elements: 1
• Number Of Channels: 8
• Number Of Inputs: 8
• Number Of Outputs: 8
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC W
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Quiescent Current: 4uA
• Technology: CMOS
• Pin Count: 20
• Mounting: Surface Mount
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1988 Fairchild Semiconductor Corporation
74AC541, 74ACT541 Rev. 1.5.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
10.65
10.00
INDICATOR
(R0.10)
PIN ONE
8°
0°
(R0.10)
7.60
7.40
B
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
2.65 MAX
1.27
0.40
(1.40)
20
1
SEATING PLANE
DETAIL A
0.75
0.25
SCALE: 2:1
0.35
0.51
0.25
13.00
12.60
11.43
X 45°
GAGE PLANE
0.25
M
C
B
A
1.27
0.30
0.10
11
10
NOTES: UNLESS OTHERWISE SPECIFIED
A
A) THIS PACKAGE CONFORMS TO JEDEC
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
C
7
0.10 C
MS-013, VARIATION AC, ISSUE E
FLASH OR BURRS.
LAND PATTERN RECOMMENDATION
2.25
1.27
SEE DETAIL A
SEATING PLANE
0.65
www.fairchildsemi.com
0.33
0.20
9.50