ADN2812ACPZ-RL7 Analog Devices, ADN2812ACPZ-RL7 Datasheet
ADN2812ACPZ-RL7
Specifications of ADN2812ACPZ-RL7
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ADN2812ACPZ-RL7 Summary of contents
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... Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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ADN2812 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. ...
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SPECIFICATIONS VCC = VEE = MIN MAX MIN MAX unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level ...
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ADN2812 Parameter DATA RATE READBACK ACCURACY Coarse Readback Fine Readback POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert ...
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OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Single-Ended Output Swing Differential Output Swing Output High Voltage Output Low Voltage CML Outputs Timing Rise Time Fall Time Setup Time Hold Time 2 I C® INTERFACE DC ...
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ADN2812 ABSOLUTE MAXIMUM RATINGS VCC = VEE = MIN MAX MIN MAX SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) ...
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TIMING CHARACTERISTICS CLKOUTP DATAOUTP/N OUTP V OUTN OUTP – OUTN Figure 2. Output Timing CML DIFF Figure 3. Single-Ended vs. Differential Output Specifications Rev Page ADN2812 V ...
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ADN2812 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Type 1 TEST1 2 VCC P 3 VREF AO 4 NIN AI 5 PIN AI 6 SLICEP AI 7 SLICEN AI 8 VEE P 9 THRADJ ...
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TYPICAL PERFORMANCE CHARACTERISTICS 100 1k R (Ω) Thresh Figure 5. LOS Comparator Trip Point Programming 1000 100 10 1 0.1 10k 100k 1 Figure 6. Typical Measured Jitter Tolerance OC-48 ...
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ADN2812 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 ...
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Table 6. Internal Register Map Reg. Name R/W Address FREQ0 R 0x00 FREQ1 R 0x01 FREQ2 R 0x02 RATE R 0x03 MISC R 0x04 CTRLA W 0x08 CTRLA_RD R 0x05 CTRLB W 0x09 CTRLB_RD R 0x06 CTRLC W 0x11 ...
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ADN2812 TERMINOLOGY INPUT SENSITIVITY AND INPUT OVERDRIVE Sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 12. For ...
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JITTER SPECIFICATIONS The ADN2812 CDR is designed to achieve the best bit-error- rate (BER) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equip- ment defined in the Telcordia Technologies GR-253-CORE document. Jitter is the dynamic ...
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ADN2812 THEORY OF OPERATION The ADN2812 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that ...
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At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of ...
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ADN2812 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION The ADN2812 acquires frequency from the data over a range of data frequencies from 12.3 Mb/s to 2.7 Gb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming ...
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LOL 1 –1000 –250 0 250 Figure 20. Transfer Function of LOL LOL Detector Operation Using a Reference Clock (REFCLK Mode) In REFCLK mode, a reference clock is used as an acquisition aid to lock the ADN2812 VCO. Lock to ...
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ADN2812 INTERFACE 2 The ADN2812 supports a 2-wire, I C-compatible, serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is ...
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The two uses of the reference clock are mutually exclusive. The reference clock can be used either as an acquisition aid for the ADN2812 to lock onto data or to measure the frequency of the incoming data to within 0.01%. ...
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ADN2812 Prior to reading back the data rate using the reference clock, Control Register CTRLA Bits[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then ...
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APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ...
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ADN2812 Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, DATAOUTN (also REFCLKP, REFCLKN high frequency reference clock is used, such ...
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VCC TIA 1 V1 V1b V2 V2b V DIFF V = V2–V2b DIFF VTH = ADN2812 QUANTIZER THRESHOLD NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. 2. WHEN THE OUTPUT ...
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ADN2812 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 14. Code F Code MID 0 5.1934e+ 5.1930e+ 5.2930e+ 5.3989e+ 5.5124e+ 5.6325e+06 53 ...
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Code F Code MID 192 3.3238e+08 216 193 3.3235e+08 217 194 3.3876e+08 218 195 3.4553e+08 219 196 3.5279e+08 220 197 3.6048e+08 221 198 3.6872e+08 222 199 3.7757e+08 223 200 3.8703e+08 224 201 3.9742e+08 225 202 4.0844e+08 226 203 4.2032e+08 227 ...
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... Temperature Range ADN2812ACP −40°C to 85°C ADN2812ACP-RL −40°C to 85°C ADN2812ACP-RL7 −40°C to 85°C 1 ADN2812ACPZ −40°C to 85°C 1 ADN2812ACPZ-RL −40°C to 85°C 1 ADN2812ACPZ-RL7 −40°C to 85°C 1 EVAL-ADN2812-EBZ RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 ...
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NOTES Rev Page ADN2812 ...
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... ADN2812 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...