ZL50402 Zarlink Semiconductor, ZL50402 Datasheet
ZL50402
Related parts for ZL50402
ZL50402 Summary of contents
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... ZL50402 MII 2-Port 10/100M + 1G Ethernet Switch GPSI Dual 10/100 PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. ZL50402 Managed 2 - Port 10/100 M + Data Sheet June 2005 Ordering Information 208-Ball LBGA 208-Ball LBGA* *Pb Free Tin/Silver/Copper -40°C to +85° EEPROM 10/100/ ...
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... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50402 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50402 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). ...
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... Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ZL50402 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... JTAG Test Clock (TCK) Speed Requirements 9.2 Clock Generation 9.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2.3 Ethernet Interface Clocks 10.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 IEEE 802.3 HUB Management (RFC 1516 10.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2.1.3 FCSErrors 10.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2.1.6 ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ZL50402 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.1.9 Jabbers 10.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1 ZL50402 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.2 INDEX_REG1 (only needed for 8-bit mode 11.2.3 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.4 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.5 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.6 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.2.7 Control Command Frame Buffer1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11 ...
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... USER_PROTOCOL_FORCE_DISCARD – User Define Protocol 0~7 Force Discard . . . . 90 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.3.5.22 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . 91 11.3.5.23 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . 91 11.3.5.24 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 91 ZL50402 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... QOSC00, QOSC01 - Classes Byte Limit port 103 11.3.8.10 QOSC02, QOSC03 - Classes Byte Limit port 103 11.3.8.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port 103 11.3.8.12 QOSC22 - QOSC27 - Classes Byte Limit GMAC port . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.3.8.13 QOSC28 - QOSC31 - Classes WFQ Credit For GMAC . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ZL50402 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Reverse General Purpose Serial Interface (RvGPSI 127 12.4.11 Gigabit Media Independent Interface (GMII 128 12.4.12 MII Management Data Interface (MDIO/MDC 130 12.4.13 JTAG (IEEE 1149.1-2001 131 13.0 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ZL50402 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...
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... August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.5 November 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.6 January 2005 133 13.7 June 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ZL50402 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...
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... RSVD RSVD R RSVD RSVD RSVD RSVD RSVD T RSVD RSVD RSVD RSVD RSVD 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 D5, D12, E4, E13, M4, M13, N5 D9, H4, H13, N7 ZL50402 P_DAT P_DAT P_DAT P_DAT P_DAT A11 P_DAT P_DAT P_DAT P_DAT P_DAT A2 A4 ...
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... J4, K3, K2, K1, F4, F3, M[1:0]_RXD[3:0] Input G2, G1 L1, H1 M[1:0]_CRS_DV Input L2, H2 M[1:0]_TXEN ZL50402 Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Input & Output signal with Tri-State driver Weak internal pull-up (nominal 100K ohm) (refer to Section 1.4 on page 17 as some internal ...
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... M9_RXD[7:0] F14, F13, G14, G13 A16 M9_TXEN B15 M9_TXER A15 M9_MTXCLK A14 M9_TXCLK ZL50402 I/O Output, slew Ports [1:0] – Transmit Data Bit [3:0] Input Ports[1:0] – Collision with pull-down Input or Output Ports[1:0] – Transmit Clock with pull-up This pin in an output if ECR4Pn[1:0]='11' Input or Output Ports[1:0] – ...
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... SS K7-10 Misc. D1 RESIN# C1 RESETOUT# F1 M_MDC F2 M_MDIO R7 M_CLK A13 GREF_CLK ZL50402 I/O Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Input JTAG - Test Data In with pull-up Input JTAG - Test Reset with pull-up Input ...
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... Bootstrap Pins External pull-up/down resistors are required on all bootstrap pins for proper operation. See “Bootstrap Options” on page 20 for more information. D2 TSTOUT[0] C3, D3, C2 TSTOUT[3:1] ZL50402 I/O N/A Reserved. Leave unconnected. IC_GND Internal Connect. Tie to ground (V resistor. Input (Reset Only) Enable Debounce on SSI interface Pullup – ...
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... C11, C10, D10 TSTOUT[15:13] L2, H2 M[1:0]_TXEN A16, B15 M9_TXEN, M9_TXER 1. Note: 1=pull-up; 0=pull-down ZL50402 I/O Input (Reset Only) Device ID. Default address of the device for serial interface device can be sharing the serial management bus with different device ID. A one (1) indicates pullup. A zero (0) indicates pulldown ...
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... Signal Mapping and Internal pull-up/Down Configuration The ZL50402 Fast Ethernet access ports (0-1) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull-up/down resistor is present for each pin in the specific operating mode ...
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... The ZL50402 Gigabit Ethernet uplink port (port 9) supports 2 interface options: GMII & MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. ...
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... The ZL50402 CPU access support 5 interface options 16-bit parallel, serial+MII (port 8), serial only, and unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. ...
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... Also, in unmanaged mode, an optional I the device at power-up or reset. TSTOUT[7] selects the EEPROM option. The ZL50402 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[1:0]_TXEN (ports 0-1) and M9-TXEN & M9_TXER (port 9) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...
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... Default Switch Configuration and Initialization Sequence The ZL50402 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic MAC address learning. In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be changed using the optional EEPROM. • ...
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... Statistics counters disabled • DiffServ EF code support disabled • No VLAN ID hashing • Per-port Defaults • CPU Port - 100 M, Full Duplex, Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ZL50402 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Power Sequencing The ZL50402 has two separate power supplies: V sequence is for applied first, followed by the V CC but by no more than 2V. Both supplies may be powered-down simultaneously. >0 RESIN SCLK See “Typical Reset & Bootstrap Timing Diagram” on page 118 for more details on reset and bootstrap sampling. ...
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... Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50402 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...
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... Frame Engine (FE) and the external physical device (PHY). The GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1G. The GMAC of the ZL50402 device meets the IEEE 802.3Z specification able to operate in 10 M/100 M either Half or Full Duplex mode with a back pressure/flow control mechanism Full duplex mode with flow control mechanism ...
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... Timeout Reset Monitor The ZL50402 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin (TSTOUT12). It also requires some register configuration via the CPU interface. ...
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... The CPU interface provides for easy and effective management of the switching system. Figure 3 on page 28 provides an overview of the 8/16-bit interface. Figure 4 on page 29 provides an overview of the SSI interface. Figure 5 on page 30 provides an overview of the SSI+MII interface. ZL50402 ISA Interface Serial 16-bit ...
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... Reg (Addr = 0) 8-bit only ) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access Figure 3 - Overview of the 8/16-bit Interface ZL50402 Processor 3-bit Address 8/16-bit Data Bus Bus Address I/O Data MUX Command/ CPU Frame Reg Interrupt Reg Status Reg (Addr = 3) (Addr = 5) ...
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... Address CPU f rame Internal Transmit CPU f rame Registers Receiv e Inderect FIFO Access Figure 4 - Overview of the SSI Interface Zarlink Semiconductor Inc. ZL50402 Serial In Strobe Interrupt 16-bit Data Bus INT I/O Data MUX Command/ Control Command Interrupt Reg Status Reg 1 Reg (Addr = 5) ...
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... Register Configuration The ZL50402 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: • ...
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... To transmit a frame from the CPU with MII interface: • ZL50402 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive clock to send packets to ZL50402 • ZL50402 has the ability to halt the receive clock if the receive FIFO of ZL50402 is overflow. Transmitting from CPU to ZL50402 will resume once the receive FIFO of ZL50402 is no longer overflow • ...
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... I C Interface The I²C interface serves the function of configuring the ZL50402 at boot time. The master is the ZL50402, and the slave is the EEPROM memory. The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch ...
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... I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time bits are used to allow up to eight ZL50402 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. ...
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... Data to be written or read back Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50402. Read operation can only be aborted before issuing the read command to the ZL50402. A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low when STROBE- fall ...
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... RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the GMAC and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the ZL50402 35 Zarlink Semiconductor Inc. ...
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... Basic Flow Shortly after a frame enters the ZL50402 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...
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... Broadcast, unknown unicast or unknown multicast MAC address can also be filter on per VLAN basis. MAC address filtering allows the ZL50402 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...
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... Extensive core QoS mechanisms are built into the ZL50402 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50402, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class ...
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... Definition” on page 60). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50402 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50402 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...
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... In addition, coordinating VLAN IDs across multiple switches enables VLANs to extend to multiple switches VLANs are supported in the ZL50402. When tag-based VLAN is enabled, each MAC address is learned with it associated VLAN. ...
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... IEEE 802.1Q Tag TPID = 0x8100 * Provider Tag TPID = Configurable on per device basis The value of the TPID of the Provider VLAN tag is not assigned in the IEEE 802.1ad standard. The ZL50402 provides a global configurable TPID but only supports the Extreme EtherType TPID (i.e. the stacked VLAN tag cannot equal 0x81-00) ...
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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50402 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...
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... Table 8 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. GMAC port actually has four total transmission priorities. ZL50402 43 Zarlink Semiconductor Inc. ...
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... It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50402, each RMAC port will support two total classes, and the GMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section ...
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... Although traffic shaping is not a primary function of the ZL50402, the chip does implement a shaper for every queue in the GMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50402. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling ...
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... Such a temporary region is necessary, because when the frame first enters the ZL50402, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...
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... The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. On the other hand, the ZL50402 will still prioritize the received frame disregarding the outgoing port flow control capability frame is classified as high priority still subjected to the WRED, which means the no-loss on the high priority queue is not guaranteed ...
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... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50402’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...
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... Up to two ports can be setup as mirrored ports result, the traffic (both ingress and egress specific port can be monitored by setting up both mirrored ports. Once a port is setup as mirrored port, it cannot be used for regular traffic. The mirrored port can be any port in the ZL50402. 8.2 Using port mirroring for loop back To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check the data path ...
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... Clocks 9.1 Clock Requirements 9.1.1 System Clock (SCLK) Speed Requirement SCLK is the primary clock for the ZL50402 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 2 Port 10/100M + 1 port 1000M 1-3 ports 10/100 M 9.1.2 RMAC Reference Clock (M_CLK) Speed Requirement M_CLK MHz clock used for the RMAC ports (ports 0-1) and CPU port (port 8) ...
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... The gigabit port generates an external TXCLK interface clock in GMII mode equal to the 125 MHz GREF_CLK. If the GMAC port is configured in Reverse MII mode, RXCLK is generated from GREF_CLK and is equal to GREF_CLK/2 for 100 M mode (no support for 10M Reverse MII mode). GREF_CLK needs MHz clock in this mode. ZL50402 51 Zarlink Semiconductor Inc. Data Sheet ...
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... Hardware Statistics Counters List ZL50402 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the filtering counter (detected by queue manager) ...
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... Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] U1: 16 bits counter bit [15: bits counter bit [31:16] u: ZL50402 53 Zarlink Semiconductor Inc. Data Sheet ...
Page 54
... No collisions 10.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions ZL50402 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< ...
Page 55
... Frame size: 10.2.1.9 LateEvents Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Events are also counted by collision counter ZL50402 > 64 bytes, > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’ ...
Page 56
... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 10.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. Not applicable for the ZL50402. 10.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50402 > Jabber 56 Zarlink Semiconductor Inc ...
Page 57
... No collisions: 10.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50402 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) (< BUF_LIMIT if enabled for this port) < 64 bytes, 57 Zarlink Semiconductor Inc. Data Sheet ...
Page 58
... Jabbers Counts number of frames received with size exceeding maximum frame size and with bad FCS. Frame size: Framing error No collisions ZL50402 > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) (> BUF_LIMIT if enabled for this port) don’t care don’t care < ...
Page 59
... Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50402 has other statistics counters for its own purposes. We have two counters for flow control – one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “ ...
Page 60
... Register Definition 11.1 ZL50402 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..1,8,9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...
Page 61
... Class 1 Reserve Size C2RS Class 2 Reserve Size C3RS Class 3 Reserve Size AVPML VLAN Priority Map Low AVPMM VLAN Priority Map Middle AVPMH VLAN Priority Map High Table 13 - Register Description (continued) ZL50402 CPU Addr Description (Hex) 323 324 325 329 330-336 337 338-339 33A-33E ...
Page 62
... USER_PORT_ User Define Logic Port 0 To ENABLE[7:0] 7 Enable USER_PORT_ User Define Logic Port 0 To FORCE_DISCARD[7:0] 7 Force Discard Enable RLOWL User Define Range Low Bit [7:0] Table 13 - Register Description (continued) ZL50402 CPU Addr Description (Hex) 533 540 541 542 543 550+n 558 560 ...
Page 63
... FCB Base Address Register 1 FCB_BASE_ADDR2 FCB Base Address Register 2 7. Port Mirroring Controls MIRROR_DEST_MAC0 Mirror Destination MAC Address 0 MIRROR_DEST_MAC1 Mirror Destination MAC Address 1 Table 13 - Register Description (continued) ZL50402 CPU Addr Description (Hex) 5A1 5A2 5A3 5A4 600 601 602 603 604 ...
Page 64
... BMRCn Broadcast/Multicast Rate Control n PR100_n Port Reservation for RMAC Ports (n=0..1) PR100_CPU Port Reservation for CPU Port PRG Port Reservation for GMAC Port Table 13 - Register Description (continued) ZL50402 CPU Addr Description (Hex) 702 703 704 705 706 707 708 709 70A 70B ...
Page 65
... PRTQUSST9B GMAC Port QOS and Queue Status B CLASSQOSST Class Buffer Status PRTINTCTR Buffer Interrupt Status QMCTRLn Ports Queue Control Status QCTRL Ports Queue Control Table 13 - Register Description (continued) ZL50402 CPU Addr Description (Hex) 860+n 868 869 880+n E00 E01 E02 E03 ...
Page 66
... Directly Accessed Registers 11.2.1 INDEX_REG0 • Address for indirectly accessed register addresses (8/16 bits) • Address = 0 (write only) • In 16-bit or serial mode: Address bits [15:0] • In 8-bit mode: Address bits [7:0] ZL50402 CPU Addr Description (Hex) EBB EBC EBD EC0 EC1 EC2 EC3 EC4 EC5 ...
Page 67
... Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit will be self-cleared. Bit [5]: Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. Bits [7:6]: Reserved. Must be '0' ZL50402 67 Zarlink Semiconductor Inc. Data Sheet ...
Page 68
... Data is read from the Control Command Frame Transmit Buffer1 11.2.8 Control Command Frame Buffer2 Access Register • CPU receive control frames (8/16 bits) • Address = 7 (read only) • When CPU reads this register: Data is read from the Control Command Frame Transmit Buffer2 ZL50402 68 Zarlink Semiconductor Inc. Data Sheet ...
Page 69
... SS - Spanning tree state (IEEE 802.1D spanning tree protocol Blocking Listening Learning Forwarding: Port 8: (CPU Port) 8/16-bit or Serial Only Modes Bit [5:0] Reserved ZL50402 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 69 Zarlink Semiconductor Inc. Data Sheet ...
Page 70
... Bit [1]: Filter Tag frame 0: Disable (Default) 1: All tagged frames from this port are discarded or follow security option when security is enable ZL50402 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) Frame is dropped Frame is dropped Frame is dropped ...
Page 71
... Disable (Default) 1: Enable Bits [7:6] Security Enable. The ZL50402 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. • ...
Page 72
... This is not the same as an ingress MAC loopback. The destination MAC address has to be stored (learned) in the MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Reserved. Must be 0. ZL50402 72 Zarlink Semiconductor Inc. Data Sheet ...
Page 73
... Reset. Not self clearing. Port 9: (GMAC Port) Bit [0]: Enable PHY Mode 00: MAC Mode (Default) 11: PHY Mode (Reverse MII) Only valid in MII interface mode. In PHY mode, M9_RXCLK pin becomes an output and M9_MTXCLK must be tied to M9_RXCLK externally. ZL50402 73 Zarlink Semiconductor Inc. Data Sheet ...
Page 74
... Accessed by CPU (R/W) Bits [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Bit [7]: Reserved 11.3.1.6 FCC – Flow Control Grant Period CPU Address:h037 Accessed by CPU (R/W) Bits [2:0]: Flow Control Grant Period. (Default 0x3) Units are (FCC[2:0]+1)*4us ZL50402 74 Zarlink Semiconductor Inc. Data Sheet ...
Page 75
... VLAN then PVID is used to replace the packet’s VLAN ID. 11.3.2.4 PVMAP00_1 – Port 0 Configuration Register 1 I²C Address h34, CPU Address:h103 Accessed by CPU and I²C (R/W) In Port based VLAN Mode Bits [1:0]: VLAN Mask for ports (Default 0x3) Bits [7:2]: Reserved (Default 0x3F) ZL50402 75 Zarlink Semiconductor Inc. Data Sheet ...
Page 76
... Force untag out (VLAN tagging is based on IEEE 802.1Q rule Disable (Default Force untagged output. All packets transmitted from this port are untagged. This bit is used when this port is connected to legacy equipment that does not support VLAN tagging. ZL50402 76 Zarlink Semiconductor Inc. Data Sheet ...
Page 77
... Enable - Learning disabled port will not receive any flooding packets (Default) 1: Disable Bit [4]: Support MAC address 0 0: MAC address 0 is not learned. (Default) This means packet with destination MAC address 0 is forwarded as unknown destination subjected to unicast to multicast rate control. 1: MAC address 0 is learned. ZL50402 77 Zarlink Semiconductor Inc. Data Sheet ...
Page 78
... CPU Address:h301 Accessed by CPU (R/W) Bits [7:0]: Byte 1 (bits [15:8]) of the CPU MAC address (Default 0) 11.3.3.3 MAC2 – CPU MAC address byte 2 CPU Address:h302 Accessed by CPU (R/W) Bits [7:0]: Byte 2 (bits [23:16]) of the CPU MAC address (Default 0) ZL50402 MAC3 MAC2 MAC1 MAC0 78 Zarlink Semiconductor Inc. Data Sheet 0 (MC bit) ...
Page 79
... Device Timeout Detected interrupt 11.3.3.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1 CPU Address:h310 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00 Mask the interrupt ZL50402 79 Zarlink Semiconductor Inc. Data Sheet ...
Page 80
... Bit [3]: Select Queue 3 Bit [4]: Select Multicast Queue 0 Bit [5]: Select Multicast Queue 1 Bit [6]: Select Multicast Queue 2 Bit [7]: Select Multicast Queue 3 Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0). ZL50402 80 Zarlink Semiconductor Inc. Data Sheet ...
Page 81
... CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command CPU Address:h330-336 Accessed by CPU, (R/W) 55 CQ6 CQ5 CPU Queue insertion command Bit[1:0]: Destination Map (port 1-0). Bit[7:2]: Reserved. Must be 0. Bit[9:8]: Destination Map (GMAC, CPU). Bits [13:10] Priority ZL50402 CQ4 CQ3 CQ2 81 Zarlink Semiconductor Inc. Data Sheet 0 CQ1 CQ0 ...
Page 82
... Bit [15]: 11.3.3.17 CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status CPU Address:h33A-33E Accessed by CPU, (R/W) CR4 CPU Queue insertion command Header pointer Bits [14:0]: Tail pointer Bits [30:15] Number of granules for the release Bits [38:32] ZL50402 15 0 CG1 CG0 CR3 CR2 CR1 CR0 82 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 83
... AGETIME_LOW – MAC address aging time Low I²C Address h049; CPU Address:h400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50402 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C) 11 ...
Page 84
... Select VLAN Tag priority field over TOS (Default) 1 – Select TOS over VLAN tag priority field Bit [6]: Select TOS bits for Priority 0 – Use TOS [4:2] bits to map the transmit priority (Default) 1 – Use TOS [7:5] bits to map the transmit priority ZL50402 84 Zarlink Semiconductor Inc. Data Sheet ...
Page 85
... I²C Address 090, CPU Address 513 2 Accessed by CPU and I C (R/W) Bits [3:0]: Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. Bits [7:4]: Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. See Programming QoS Registers application note, ZLAN-42, for more information ZL50402 85 Zarlink Semiconductor Inc. Data Sheet ...
Page 86
... Class 1 FCB Reservation Buffer reservation for class 1. Granularity 16 granules . (Default 0) 11.3.5.10 C2RS – Class 2 Reserve Size I²C Address h076, CPU Address 51A Accessed by CPU and I²C (R/W) Bits [7:0]: Class 2 FCB Reservation Buffer reservation for class 2. Granularity 16 granules . (Default 0) ZL50402 86 Zarlink Semiconductor Inc. Data Sheet ...
Page 87
... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50402. When the packet goes out it carries the original priority. Bits [2:0]: ...
Page 88
... Map TOS field in IP packet into eight level transmit priorities Bit [0]: Priority when the TOS field is 2 (Default 0) Bits [3:1]: Priority when the TOS field is 3 (Default 0) Bits [6:4]: Priority when the TOS field is 4 (Default 0) Bit [7]: Priority when the TOS field is 5 (Default 0) ZL50402 88 Zarlink Semiconductor Inc. Data Sheet ...
Page 89
... Frame drop priority when TOS field is 7 (Default 0) 11.3.5.20 USER_PROTOCOL_n – User Define Protocol 0~7 I²C Address h0B3+n, CPU Address:h550+n Accessed by CPU and I²C (R/W) (Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight separate protocols. Bits [7:0]: User Define Protocol ZL50402 89 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50402 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...
Page 91
... WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority I²C Address h0AB, CPU Address 563 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Bits [7:4]: Priority setting, transmission + dropping, for Well known port 7 (554 for rtsp) ZL50402 91 Zarlink Semiconductor Inc. Data Sheet ...
Page 92
... Bit [3]: Enable Well Known Port 3 Force Discard Bit [4]: Enable Well Known Port 4 Force Discard Bit [5]: Enable Well Known Port 5 Force Discard Bit [6]: Enable Well Known Port 6 Force Discard Bit [7]: Enable Well Known Port 7 Force Discard ZL50402 92 Zarlink Semiconductor Inc. Data Sheet ...
Page 93
... USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority I²C Address h0A4, CPU Address 592 Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for logic port 4 Bits [7:4]: Priority setting, transmission + dropping, for logic port 5 (Default 00) ZL50402 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High 93 Zarlink Semiconductor Inc. ...
Page 94
... Enable User Port 2 Force Discard Bit [3]: Enable User Port 3 Force Discard Bit [4]: Enable User Port 4 Force Discard Bit [5]: Enable User Port 5 Force Discard Bit [6]: Enable User Port 6 Force Discard Bit [7]: Enable User Port 7 Force Discard ZL50402 94 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [0]: Drop Priority (inclusive only) Bits [3:1] Transmit Priority (inclusive only) Bits [5:4] Reserved Bits [7: Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH Inclusive Filtering (RLOW<x<RHIGH Invalid ZL50402 95 Zarlink Semiconductor Inc. Data Sheet ...
Page 96
... Accessed by CPU and I²C (R/W) Bit [0]: Statistic Counter 0 – Disable (Default) 1 – Enable (all ports) When statistic counter is enable, an interrupt control frame is generated to the CPU, every time a counter wraps around. This feature requires an external CPU. Bit [1]: 0 ZL50402 96 Zarlink Semiconductor Inc. Data Sheet ...
Page 97
... Bits [7:0]: MII Command Data [7:0] Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 11.3.6.5 MIIC1 – MII Command Register 1 CPU Address:h604 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [15:8] ZL50402 97 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... MII command. Writing this register will initiate a serial management cycle to the MII management interface. 11.3.6.8 MIID0 – MII Data Register 0 CPU Address:h607 Accessed by CPU (RO) Bits [7:0]: MII Data [7:0] 11.3.6.9 MIID1 – MII Data Register 1 CPU Address:h608 Accessed by CPU (RO) Bits [7:0]: MII Data [15:8] ZL50402 98 Zarlink Semiconductor Inc. Data Sheet ...
Page 99
... The checksum formula is: FF Σ I²C register = When the ZL50402 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50402 does not start and pin CHECKSUM_OK is set to zero. ZL50402 99 Zarlink Semiconductor Inc. ...
Page 100
... MIRROR CONTROL – Port Mirror Control Register CPU Address 70C Accessed by CPU (R/W) (Default 00) Bits [3:0]: Destination port to be mirrored to. Bit [4] Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0] Bit [5] Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0] Bit [6]: Mirror when address is destination Bit [7]: Mirror when address is source ZL50402 100 Zarlink Semiconductor Inc. Data Sheet ...
Page 101
... Mirror enable 11.3.7.5 RMII_MIRROR1 – RMII Mirror 1 CPU Address 711 Accessed by CPU (R/W) Bits [2:0]: Source port to be mirrored Bit [3]: Mirror path 0: Receive 1: Transmit Bits [6:4]: Destination port for mirrored traffic Bit [7]: Mirror enable ZL50402 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] ...
Page 102
... I²C Address h06A+n, CPU Address 840 port number) Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. (Default 0x6) 11.3.8.4 PR100_CPU – Port CPU Reservation I²C Address h073, CPU Address 848 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. (Default 0x6) ZL50402 102 Zarlink Semiconductor Inc. Data Sheet ...
Page 103
... QOSC16 – BYTE_L11 Level 1 for queue 1 (I • QOSC17 – BYTE_L21 Level 2 for queue 1 (I • QOSC18 – BYTE_L12 Level 1 for queue 2 (I ZL50402 2 C Address h088, CPU Address 890 Address h089, CPU Address 891 Address h08A, CPU Address 892) 103 Zarlink Semiconductor Inc ...
Page 104
... W0 – QOSC36[7:0] – TOKEN_LIMIT_C00 (CPU Address 8A4) W1 – QOSC37[7:0] – TOKEN_LIMIT_C01 (CPU Address 8A5) W2 – QOSC38[7:0] – TOKEN_LIMIT_C02 (CPU Address 8A6) W3 – QOSC39[7:0] – TOKEN_LIMIT_C03 (CPU Address 8A7) ZL50402 2 C Address h08B, CPU Address 893 Address h08C, CPU Address 894) ...
Page 105
... CPU Address E10-E14 Accessed by CPU (R/W) Disable timeout reset on selected state machine status. See Programming Timeout Reset application note, ZLAN-41, for more information. 11.3.9.5 BOOTSTRAP0 – BOOTSTRAP3 CPU Address E80-E83 Accessed by CPU (RO) 31 BT3 ZL50402 23 15 BT2 BT1 105 Zarlink Semiconductor Inc. Data Sheet 0 BT0 ...
Page 106
... Bit [7]: 11.3.9.7 PRTQOSST0-PRTQOSST1 CPU Address EA0+n Accessed by CPU (RO) Source port reservation low Bit [0]: No source port buffer left Bit [1]: Unicast congestion detected on best effort queue Bit [2]: Reserved Bit [3]: High priority queue reach L1 WRED level Bit [4]: ZL50402 106 Zarlink Semiconductor Inc. Data Sheet ...
Page 107
... MC queue full Bit [13]: Priority 3 MC queue full Bits [15:14]: Reserved 11.3.9.9 PRTQOSST9A, PRTQOSST9B (GMAC port) CPU Address EAA – EAB Accessed by CPU (RO) Bit [0]: Source port reservation low Bit [1]: No source port buffer left ZL50402 PQSTB PQSTA 15 PQSTB PQSTA 107 Zarlink Semiconductor Inc. Data Sheet 0 0 ...
Page 108
... Bit [1]: Interrupt when no source buffer Bit [2]: Interrupt when UC congest Bit [3]: Interrupt when L1 WRED level Bit [4]: Interrupt when L2 WRED level Bit [5]: Interrupt when MC queue full Bit [6]: Interrupt when LHB timeout Bit [7]: Interrupt when no class buffer ZL50402 108 Zarlink Semiconductor Inc. Data Sheet ...
Page 109
... BMBISTR0, BMBISTR1 CPU Address EBB, EBC Accessed by CPU (RO) 11.3.9.15 BMControl CPU Address EBD Accessed by CPU (R/W) Bits [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Bits [7:4]: Reserved ZL50402 109 Zarlink Semiconductor Inc. Data Sheet ...
Page 110
... Bits [7:0] CPU address EC2 Accessed by CPU (R/W) Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Bits [6:0] Set 1 to write Bit [7] If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. ZL50402 110 Zarlink Semiconductor Inc. Data Sheet ...
Page 111
... The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from ZL50402 111 Zarlink Semiconductor Inc. ...
Page 112
... Accessed by CPU (RO) Bits [4:0] Rls_count[6:2] Bit [ then It is multicast packet. Bits [7:6] Rls_src_port[1:0[ CPU address ECD Accessed by CPU (RO) Bits [1:0] Rls_src_port[3:2] Bits [3:2] Class[1:0] Bit [4] This release request is from QM directly. Bits [7:5] Entries count in release FIFO, 0 means FIFO is empty ZL50402 112 Zarlink Semiconductor Inc. Data Sheet ...
Page 113
... Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bits [5:4]: Device Signature 11: ZL50402 device Bits [7:6]: Revision 00: Initial Silicon 01: Second Silicon ZL50402 113 Zarlink Semiconductor Inc. Data Sheet ...
Page 114
... Full duplex port 1: Full duplex 0: Half duplex Bit [2] Fast Ethernet port (if bit [5] not set Port Bit [3] Link is down 1: Link down 0: Link up Bit [4] Auto negotiation disabled 1: Disable 0: Enable Bit [5] Gigabit Ethernet port 1: GE Port ZL50402 114 Zarlink Semiconductor Inc. Data Sheet ...
Page 115
... Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit will always be ‘1’. 11.3.10.6 DA – Dead or Alive Register CPU Address: hFFF Accessed by CPU (RO) Always return 8’ Indicate the CPU interface or serial port connection is good. Bits [7:0] Always return DA ZL50402 115 Zarlink Semiconductor Inc. Data Sheet ...
Page 116
... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 12.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50402 -65 ° +150 ° C -40 ° +85 ° C +125 ° C +2. +3. +1. + ...
Page 117
... OUT C I/O Capacitance I/O θ Thermal resistance with 0 air flow ja θ Thermal resistance with 1 m/s air flow ja θ Thermal resistance with 2 m/s air flow ja θ Thermal resistance between junction and case jc ZL50402 Min. 2.4 2.0 < < OUT CC 117 Zarlink Semiconductor Inc. Data Sheet Typ. Max. ...
Page 118
... R1 Bootstrap Pins Outputs Figure 13 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50402 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor 1 µ µ s Bootstrap pins sampled on rising edge of ...
Page 119
... Description Write Cycle Symbol Write Set up Time T Write Active Time T Write Hold Time T Write Recovery time T Data Set Up time T Data Hold time T ZL50402 Activ e Tim e R ecov ery Tim ATA0 H old tim e (SCLK=100 Mhz) (SCLK=50 Mhz) Min ...
Page 120
... Description Read Cycle Symbol Read Set up Time T Read Active Time T Read Hold Time T Read Recovery time T Data Valid time T Data Invalid time T ZL50402 Activ e Tim e R ecov ery Tim ATA0 Inv alid tim e ...
Page 121
... DATAOUT output delay time D3** D4 STROBE low time D5 STROBE high time STROBE frequency of operation * Open Drain Output. Low to High transition is controlled by external pullup resistor. ** Totem Pole Output. ZL50402 Figure 16 - SSI Setup & Hold Timing D3-max D3-min Figure 17 - SSI Output Delay Timing Parameter Min ...
Page 122
... EEPROM Inter-Integrated Circuit (I²C) Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transition is controlled by external pullup resistor. ZL50402 SCL S1 SDA Figure 18 - I²C Setup & Hold Timing SCL S3-max S3-min SDA Figure 19 - I² ...
Page 123
... Reduced Media Independent Interface (RMII) Symbol M2 M[1:0]_RXD[1:0] Input Setup Time M3 M[1:0]_RXD[1:0] Input Hold Time M4 M[1:0]_CRS_DV Input Setup Time M5 M[1:0]_CRS_DV Input Hold Time M6 M[1:0]_TXEN Output Delay Time M7 M[1:0]_TXD[1:0] Output Delay Time ZL50402 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] Figure 20 - RMII Transmit Timing M_CLK M2 Mn_RXD M3 M4 ...
Page 124
... Mn_RXD[3:0] Input Setup Time MM3 Mn_RXD[3:0] Input Hold Time MM4 Mn_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time ZL50402 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Figure 22 - MII Transmit Timing Mn_RXCLK MM2 ...
Page 125
... CPU_MII_CRS_DV Input Hold Time RM6* Mn_TXEN Output Delay Time CPU_MII_TXEN Output Delay Time RM7* Mn_TXD[3:0] Output Delay Time CPU_MII_TXD[3:0] Output Delay Time * May need to add up to 8ns delay depending on other MAC device’s min. hold time. ZL50402 Mn_TXCLK RM6-max RM6-min Mn_TXEN RM7-max RM7-min Mn _TXD[3:0] ...
Page 126
... M[1:0]_RXD Input Setup Time SM3 M[1:0]_RXD Input Hold Time SM4 M[1:0]_CRS_DV Input Setup Time SM5 M[1:0]_CRS_DV Input Hold Time SM6 M[1:0]_TXEN Output Delay Time SM7 M[1:0]_TXD Output Delay Time ZL50402 Mn_TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Figure 26 - GPSI Transmit Timing Mn_RXCLK SM2 ...
Page 127
... M[1:0]_RXD Input Setup Time RS3 M[1:0]_RXD Input Hold Time RS4 M[1:0]_CRS_DV Input Setup Time RS5 M[1:0]_CRS_DV Input Hold Time RS6 M[1:0]_TXEN Output Delay Time RS7 M[1:0]_TXD Output Delay Time ZL50402 Mn_TXCLK RS6-max RS6-min Mn_TXEN RS7-max RS7-min Mn_TXD Figure 28 - RvGPSI Transmit Timing Mn_RXCLK RS2 ...
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... Gigabit Media Independent Interface (GMII) ZL50402 M9_TXCLK G12-max G12-min M9_TXD [7:0] G13-max G13-min M9_TXEN G14-max G14-min M9_TXER Figure 30 - GMII Transmit Timing M9_RXCLK M9_RXCLK G1 G2 M9_RXD[7:0] M9_RXD[7: M9_RXDV M9_RXDV G5 G6 M9_RXER M9_RXER G7 G8 M9_RX_CRS M9_RX_CRS Figure 31 - GMII Receive Timing 128 Zarlink Semiconductor Inc. ...
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... M9_RXDV Input Hold Times G5 M9_RXER Input Setup Times G6 M9_RXER Input Hold Times G7 M9_CRS Input Setup Times G8 M9_CRS Input Hold Times G12 M9_TXD[7:0] Output Delay Times G13 M9_TXEN Output Delay Times G14 M9_TXER Output Delay Times ZL50402 125 Mhz Min. (ns) Max. (ns) 2 0.5 2 0.5 2 0 129 Zarlink Semiconductor Inc ...
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... MII Management Data Interface (MDIO/MDC) Symbol D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50402 MDC D1 D2 MDIO Figure 32 - MDIO Setup & Hold Timing MDC D3-max D3-min MDIO Figure 33 - MDIO Output Delay Timing MDC=500 KHz Parameter Min. (ns) ...
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... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50402 J1 J2 Figure 34 - JTAG Timing Diagram Min. Typ. Max ...
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... Clarified that only bit [7] is not self-clearing • Updated CPU timing diagrams to clarify timing 13.5 November 2004 • Added section “Default Switch Configuration and Initialization Sequence” on page 21 • Updated CPU timing diagrams to clarify P_A timing ZL50402 132 Zarlink Semiconductor Inc. Data Sheet ...
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... Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap TSTOUT[0] • Added power sequencing recommendation (Section 1.7 on page 23) • Added Reverse MII/GPSI timing characteristics (Section 12.4.8 on page 125 and Section 12.4.10 on page 127) • Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50402 ZL50402 133 Zarlink Semiconductor Inc. Data Sheet ...
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... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN DATE 14Nov02 APPRD. BOTTOM VIEW b Previous package codes MIN MAX Dimension 1. 0.30 0.50 A2 0.53 REF D 16.90 17.10 16.90 17.10 E 0.40 0. 208 Conforms to JEDEC MO-192 Package Code ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...