S3F80JB Samsung, S3F80JB Datasheet
S3F80JB
Related parts for S3F80JB
S3F80JB Summary of contents
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... S3F80JB 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.1 ...
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... S3F80JB 8-Bit CMOS Microcontrollers User's Manual, Revision 1.1 Publication Number: 21.1-S3F-80JB-032006 © 2006 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics ...
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... Timer 2 Chapter 14 Comparator Two order forms are included at the back of this manual to facilitate customer order for S3F80JB microcontrollers: the Flash Factor Writing Order Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. ...
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... Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Series Microcontrollers ........................................................................................................... 1-1 S3F80JB Microcontroller ............................................................................................................................ 1-1 Features ..................................................................................................................................................... 1-2 Block Diagram (32-pin package) ................................................................................................................ 1-3 Block Diagram (44-pin package) ................................................................................................................ 1-4 Pin Assignments......................................................................................................................................... 1-5 Pin Circuits ................................................................................................................................................. 1-10 Chapter 2 Address Spaces Overview .................................................................................................................................................... 2-1 Program Memory........................................................................................................................................ 2-2 Register Architecture .................................................................................................................................. 2-5 Register Page Pointer (PP)................................................................................................................ 2-7 Register Set1 ..................................................................................................................................... 2-8 Register Set 2 .................................................................................................................................... 2-8 Prime Register Space ........................................................................................................................ 2-9 Working Registers ...
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... Instruction Pointer (IP) .......................................................................................................................5-17 Fast Interrupt Processing ...................................................................................................................5-17 Chapter 6 Instruction Set Overview ....................................................................................................................................................6-1 Flags Register (FLAGS).....................................................................................................................6-6 Flag Descriptions ...............................................................................................................................6-7 Instruction Set Notation......................................................................................................................6-8 Condition Codes.................................................................................................................................6-12 Instruction Descriptions ......................................................................................................................6-13 Chapter 7 Clock Circuit Overview ....................................................................................................................................................7-1 System Clock Circuit ..........................................................................................................................7-1 Clock Status During Power-Down Modes ..........................................................................................7-2 System Clock Control Register (CLKCON) ........................................................................................7-3 vi (Continued) S3F80JB MICROCONTROLLER ...
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... Back-up mode.................................................................................................................................... 8-10 Stop Mode ......................................................................................................................................... 8-11 Sources to Release Stop Mode ......................................................................................................... 8-12 System Reset Operation.................................................................................................................... 8-14 Hardware Reset Values ..................................................................................................................... 8-15 Recommendation for Unusued Pins .................................................................................................. 8-19 Summary Table of Back-Up Mode, Stop Mode, and Reset Status..................................................... 8-20 Chapter 9 I/O Ports Overview .................................................................................................................................................... 9-1 Port Data Registers............................................................................................................................ 9-4 Pull-Up Resistor Enable Registers ..................................................................................................... 9-5 S3F80JB MICROCONTROLLER (Continued) vii ...
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... Timer 1 Match interrupt ......................................................................................................................11-3 Timer 1 Control Register (T1CON).....................................................................................................11-5 Chapter 12 Counter A Overview ....................................................................................................................................................12-1 Counter A Control Register (CACON) ................................................................................................12-3 Counter A Pulse Width Calculations...................................................................................................12-4 Chapter 13 Timer 2 Overview ....................................................................................................................................................13-1 Timer 2 Overflow Interrupt..................................................................................................................13-2 Timer 2 Capture Interrupt ...................................................................................................................13-2 Timer 2 Match Interrupt ......................................................................................................................13-3 Timer 2 Control Register (T2CON).....................................................................................................13-5 Chapter 14 Comparator Overview ....................................................................................................................................................14-1 Comparator Operation .......................................................................................................................14-3 viii (Continued) S3F80JB MICROCONTROLLER ...
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... Overview······················································································································································ 20-1 Target Boards................................................................................................................................... 20-1 Programming Socket Adapter........................................................................................................... 20-1 TB80JB Target Board....................................................................................................................... 20-2 OTP/MTP Programmer (Writer)........................................................................................................ 20-7 S3F80JB MICROCONTROLLER (Continued) ix ...
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... Indexed Addressing to Program or Data Memory with Short Offset..........................3-8 3-9 Indexed Addressing to Program or Data Memory .....................................................3-9 3-10 Direct Addressing for Load Instructions ....................................................................3-10 3-11 Direct Addressing for Call and Jump Instructions .....................................................3-11 3-12 Indirect Addressing...................................................................................................3-12 3-13 Relative Addressing..................................................................................................3-13 3-14 Immediate Addressing ..............................................................................................3-14 4-1 Register Description Format .....................................................................................4-4 x List of Figures Title Page Number S3F80JB MICROCONTROLLER ...
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... RESET Block Diagram by LVD for The S3F80JB IN STOP MODE .......................... 8-4 8-4 Internal Power-On Reset Circuit ............................................................................... 8-5 8-5 Timing Diagram for Internal Power-On Reset Circuit................................................ 8-6 8-6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR ........................... 8-7 8-7 Block Diagram for Back-up Mode ............................................................................. 8-10 8-8 Timing Diagram for Back-up Mode Input and Released by LVD............................... 8-10 9-1 S3F80JB I/O Port Data Register Format ...
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... Simplified Timer 2 Function Diagram: Interval Timer Mode ......................................13-3 13-3 Timer 2 Block Diagram .............................................................................................13-4 13-4 Timer 2 Control Register (T2CON) ...........................................................................13-5 13-5 Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6 14-1 Comparator Block Diagram for The S3F80JB...........................................................14-2 14-2 Conversion Characteristics.......................................................................................14-3 14-3 Comparator Mode Register (CMOD) ........................................................................14-4 14-4 Comparator Input Selection Register (CMPSEL) ......................................................14-4 14-5 Comparator Result Register (CMPREG) ..................................................................14-5 15-1 Program Memory Address Space ...
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... Operating Voltage Range of S3F80JB ····································································· ...
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... Set 1, Bank 1 Register Values After Reset ............................................................... 8-17 8-5 Reset Generation According to the Condition of Smart Option................................. 8-18 8-6 Guideline for Unused Pins to Reduced Power Consumption.................................... 8-19 8-7 Summary of Each Mode ........................................................................................... 8-20 9-1 S3F80JB Port Configuration Overview (44-QFP) ..................................................... 9-2 9-3 S3F80JB Port Configuration Overview (32-SOP) ..................................................... 9-3 9-4 Port Data Register Summary.................................................................................... 9-4 S3F80JB MICROCONTROLLER List of Tables Title Page Number xv ...
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... Default Setting of the Jumper in S3F80JB Target Board ·········································· ...
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... Basic Timer and Timer 0 Configuring the Basic Timer ....................................................................................................................... 10-11 Programming Timer 0................................................................................................................................. 10-12 Chapter 12 Counter A To Generate 38 kHz, 1/3duty Signal Through P3.1 .................................................................................... 12-6 To Generate a one Pulse Signal Through P3.1 .......................................................................................... 12-7 Chapter 15 Embedded Flash Memory Interface Sector Erase .............................................................................................................................................. 15-10 Programming.............................................................................................................................................. 15-15 Reading...................................................................................................................................................... 15-17 Hard Lock Protection .................................................................................................................................. 15-18 S3F80JB MICROCONTROLLER List of Programming Tips Page Number xvii ...
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... Port 4 Control Register (Low Byte) ........................................................................... 4-36 PP Register Page Pointer .............................................................................................. 4-37 RP0 Register Pointer 0..................................................................................................... 4-38 RP1 Register Pointer 1..................................................................................................... 4-38 SPL Stack Pointer (Low Byte) .......................................................................................... 4-39 STOPCON Stop Control Register ............................................................................................... 4-39 SYM System Mode Register ............................................................................................. 4-40 T1CON Timer 1 Control Register .......................................................................................... 4-42 T2CON Timer 2 Control Register .......................................................................................... 4-43 S3F80JB MICROCONTROLLER Full Register Name Page Number xix ...
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... Load Bit .................................................................................................................... 6-51 LDC/LDE Load Memory ........................................................................................................... 6-52 LDC/LDE Load Memory ........................................................................................................... 6-53 LDCD/LDED Load Memory and Decrement .................................................................................. 6-54 LDCI/LDEI Load Memory and Increment.................................................................................... 6-55 LDCPD/LDEPD Load Memory with Pre-Decrement ........................................................................... 6-56 LDCPI/LDEPI Load Memory with Pre-Increment............................................................................. 6-57 LDW Load Word................................................................................................................ 6-58 MULT Multiply (Unsigned)................................................................................................... 6-59 S3F80JB MICROCONTROLLER Full Register Name Page Number xxi ...
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... Set Carry Flag ..........................................................................................................6-78 SRA Shift Right Arithmetic ................................................................................................6-79 SRP/SRP0/SRP1 Set Register Pointer .................................................................................................6-80 STOP Stop Operation .........................................................................................................6-81 SUB Subtract ....................................................................................................................6-82 SWAP Swap Nibbles............................................................................................................6-83 TCM Test Complement Under Mask .................................................................................6-84 TM Test Under Mask ......................................................................................................6-85 WFI Wait For Interrupt......................................................................................................6-86 XOR Logical Exclusive OR................................................................................................6-87 xxii Full Register Name (Continued) Page Number S3F80JB MICROCONTROLLER ...
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... One 8-bit counter with auto-reload function and one-shot or repeat control. The S3F80JB is a versatile general-purpose microcontroller, which is especially suitable for use as remote transmitter controller currently available in a 32-pin SOP and 44-pin QFP package. ...
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... When V is lower than V DD LVD Back-up mode to block oscillation and reduce the current consumption. In S3F80JB, this function is disabled when operating state is “STOP mode”. • When reset pin is lower than Input Low Voltage (V ), the chip enters Back-up mode to block IL oscillation and reduce the current consumption ...
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... S3F80JB BLOCK DIAGRAM (32-PIN PACKAGE) P0.0-0.3 (INT0-INT3) LVD V DD IPOR(note Main X OSC OUT 8-Bit Basic Timer 8-Bit Timer0 /Counter 16-Bit Timer1 /Counter 16-Bit Timer2 /Counter IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2) P0.4-P0.7(INT4) P1.0-1.7 Port0 Port1 ...
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... IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2) 1-4 P0.4-P0.7(INT4) P1.0-1.7 Port0 Port1 I/O Port and Interrupt Control SAM8RC CPU 64K-byte 272-byte FLASH Register File Memory Carrier Generator Comparator (Counter A) Figure 1-2. Block Diagram (44-pin) NOTE S3F80JB TEST nRESET P2.0-2.3 (INT5-INT8) Port2 P2.4-2.7 (INT9) (CIN0-CIN3) P3.0/T0PWM/T0CAP/SDAT P3.1/REM/SCLK Port3 P3.2/T0CK P3.3/T1CAP/T2CAP P3.4-P3.5 P4.0-P4.7 Port4 ...
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... XOUT XIN TEST P2.5/INT9/CIN1 P2.6/INT9/CIN2 nRESET P2.7/INT9/CIN3 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package S3F80JB 26 7 (Top View 32-SOP PRODUCT OVERVIEW VDD P3.1/REM/T0CK/SCLK P3.0/T0PWM/T0CAP/T1CAP/T2CAP/SDAT P2.4/INT9/CIN0 P2.3/INT8 P2 ...
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... PRODUCT OVERVIEW PIN ASSIGNMENTS (Continued) P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 P4.3 P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 Figure 1-4. Pin Assignment Diagram (44-Pin QFP Package) 1 S3F80JB 19 37 (Top View (44-QFP S3F80JB P1.3 P1.2 P1.1 P4.7 P3.3/T1CAP/T2CAP P3.2/T0CK P1.0 P2.7/INT9/CIN3 P3.5 P3.4 nRESET ...
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... S3F80JB Pin Pin Names Type I/O I/O port with bit-programmable pins. Configurable P0.0–P0.7 to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED&R (note) circuit built in P0 for STOP releasing ...
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... Refer to page 8-11. 1-8 Table 1-2. Pin Descriptions of 44-QFP Pin Description Circuit 44 Pin Shared Type No. Functions 1 30–37 Ext. INT (INT0–INT3) (INT4 – 20–26 1 42–44 Ext. INT 1, 2, (INT5–INT8) 10,11, (INT9) 15 (CIN0-CIN3 T0PWM/T0CAP (SDAT) S3F80JB ...
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... S3F80JB Table 1-2. Pin Descriptions of 44-QFP (Continued) Pin Pin Names Type P3.1 I/O I/O port with bit-programmable pin. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software. This port 3pin has high current drive capability. Also P3.1 can be assigned individually as an output pin for REM ...
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... PRODUCT OVERVIEW PIN CIRCUITS Pull-up Enable Data Output Disable P2.4-P2.7 Only External Interrupt Stop Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2) 1-10 P2CONx.x CMPSEL.0-.3 External REF (P2.7 only Comparator Noise Filter V DD Pull-Up Resistor (55kΩ- typ INPUT/OUTPUT V SS MUX REF Stop Release S3F80JB ...
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... S3F80JB PIN CIRCUITS (Continued) Pull-up Enable Data Open-Drain Output Disable Normal Input Figure 1-6. Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3. Pull-up Resistor (55kΩ-Typ INPUT/OUTPUT V SS Noise Filter PRODUCT OVERVIEW 1-11 ...
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... PRODUCT OVERVIEW PIN CIRCUITS (Continued) Pull-up Enable Port 3.0 Data T0_PWM Open-Drain Output Disable P3.0 Input T0CAP/(T1CAP/T2CAP) 1-12 P3CON Data P3CON.2,6 Noise filter X Figure 1-7. Pin Circuit Type 3 (P3. Pull-up Resistor (55kΩ-Typ) P3.0/T0PWM T0CAP/ (T1CAP/T2CAP) S3F80JB ...
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... S3F80JB PIN CIRCUITS (Continued) Pull-up Enable Port 3.1 Data Carrier On/Off (P3.7) CACON.2 Open-Drain Output Disable P3.1 Input Input T0CK : P3.2 T1CAP/T2CAP: P3.3 P3CON.5 M Data U X P3CON.5,6,7 M T0CK U Noise filter X Figure 1-8. Pin Circuit Type 4 (P3.1) P3CON.2,6 Figure 1-9. Pin Circuit Type 5 (P3.2 and P3.3) PRODUCT OVERVIEW V DD Pull-up Resistor (55kΩ ...
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... PRODUCT OVERVIEW PIN CIRCUITS (Continued) 1-14 Figure 1-10. Pin Circuit Type 6 (nRESET Pull-up Resistor (500kΩ-Typ) nRESET S3F80JB ...
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... A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3F80JB has a programmable internal 64-Kbytes Flash ROM. An external memory interface is not implemented. There are 333 mapped registers in the internal register file. Of these, 272 are for general-purpose use. ( This number includes a 16-byte working register common area that is used as a “ ...
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... S3F80JB PROGRAM MEMORY Program memory (Flash memory) stores program code or table data. The S3F80JB has 64-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–FFFFH of Flash memory (See Figure 2-1). The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (0000H – ...
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... Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable) ...
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... S3F80JB 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H) ...
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... In case of S3F80JB the total number of addressable 8-bit registers is 333. Of these 333 registers, 22 bytes are for CPU and system control registers, 39 bytes are for peripheral control and data registers, 16 bytes are used as shared working registers, and 272 registers are for general-purpose use ...
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... S3F80JB FFH Control Register (Register Addressing 64 Bytes E0H DFH System Register (Register Addressing D0H CFH Working Register (Working Register Addressing only) C0H 2-6 Set 1 Bank1 Bank 0 32 System and Bytes Peripheral Mode) E0H Mode) 32 Bytes 192 Bytes Figure 2-3. Internal Register File Organization ...
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... Page addressing is controlled by the register page pointer PP (DFH, Set 1, Bank0). In the S3F80JB microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to “page 0”. ...
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... The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3F80JB microcontroller, bank 1 is implemented. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte area of set 1, bank 0, (E0H– ...
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... S3F80JB PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers the case for set 1 and set 2 registers.). ...
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... S3F80JB WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers. ...
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... S3F80JB USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH. ...
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... S3F80JB RP0 RP1 Figure 2-8. Non-Contiguous 16-Byte Working Register Block PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H ...
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... S3F80JB REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space ...
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... After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). NOTE: In the S3F80JB microcontroller,only page0 is implemented.Page0 containsall of the addressable registers in the internal register file. 00H 2-14 ...
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... S3F80JB COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file ...
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... S3F80JB PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Example 1: LD 0C2H,40H Use working register addressing instead: SRP #0C0H ...
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... S3F80JB Register pointer provides five high-order bits Figure 2-12. 4-Bit Working Register Addressing RP0 Figure 2-13. 4-Bit Working Register Addressing Example Selects RP0 or RP1 Address OPCODE 4-bit address procides three low-order bits Together they create an ...
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... S3F80JB 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing ...
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... S3F80JB Specifies working register addressing Figure 2-15. 8-Bit Working Register Addressing Example RP0 Selects RP1 R11 8-bit address from instruction 'LD R11, R2' Register address (0ABH) 1 ADDRESS SPACES RP1 2-19 ...
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... Stack Pointers (SPL) Register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in The S3F80JB, the SPL must be initialized to an 8-bit value in the range 00–FFH. ...
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... S3F80JB PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH • • • PUSH PP PUSH RP0 PUSH RP1 PUSH R3 • ...
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... S3F80JB 3 ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in instructions may be condition codes, immediate data location in the register file, program memory, or data memory ...
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... MSB Points to RP0 ot RP1 3 LSBs src Points to the woking register ( R1 Where R1 and R2 are registers in the curruntly selected working register area. Figure 3-2. Working Register Addressing Register File OPERAND Register File RP0 or RP1 Selected RP points to start of working register block OPERAND S3F80JB ...
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... S3F80JB INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM external memory space, if implemented (see Figures 3-3 through 3-6). ...
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... INDIRECT REGISTER ADDRESSING MODE (Continued) Program Memory Example Instruction References OPCODE Program Memory Sample Instructions: CALL @RR2 JP @RR2 Figure 3-4. Indirect Register Addressing to Program Memory 3-4 dst Points to Register Pair Value used in instruction Register File Register Pair 16-Bit Address Points to Program Program Memory Memory OPERAND S3F80JB ...
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... S3F80JB INDIRECT REGISTER ADDRESSING MODE (Continued) Program Memory 4-bit Working dst Register OPCODE Address Sample Instruction: OR R3, @R6 Figure 3-5. Indirect Working Register Addressing to Register File Register File MSB Points to RP0 or RP1 RP0 or RP1 ~ 3 LSBs src Point to the Woking Register ( Value used in ...
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... References either Program Memory or Data Memory Sample Instructions: LCD LDE LDE NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-6. Indirect Working Register Addressing to Program or Data Memory 3-6 MSB Points to RP0 or RP1 dst src Next 2-bit Point OPCODE ...
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... S3F80JB INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented). You cannot, however, access locations C0H– ...
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... Register Address OPCODE Sample Instructions: LDC R4, #04H[RR2] LDE R4,#04H[RR2] NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset 3-8 MSB Points to RP0 or RP1 OFFSET NEXT 2 BITS x Point to Working Register Pair ...
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... Register Address OPCODE Sample Instructions: LDC R4, #1000H[RR2] LDE R4,#1000H[RR2] NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-9. Indexed Addressing to Program or Data Memory MSB Points to RP0 or RP1 OFFSET OFFSET NEXT 2 BITS x Point to Working Register Pair ...
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... Load operations to program memory (LDC external data memory (LDE), if implemented. Sample Instructions: LDC R5,1234H LDE R5,1234H NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-10. Direct Addressing for Load Instructions 3-10 Program or Data Memory Memory Address Program Memory ...
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... S3F80JB DIRECT ADDRESS MODE (Continued) Sample Instructions: JP C,JOB1 CALL DISPLAY Figure 3-11. Direct Addressing for Call and Jump Instructions Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE ; Where JOB1 is a 16-bit immediate address ; Where DISPLAY is a 16-bit immediate address ...
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... Instruction Sample Instruction: CALL #40H 3-12 Program Memory Next Instruction LSB Must be Zero dst OPCODE Lower Address Byte Upper Address Byte ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address. Figure 3-12. Indirect Addressing S3F80JB Program Memory Locations 0-255 ...
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... S3F80JB RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction ...
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... In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. 3-14 Program Memory OPERAND OPCODE (The operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-14. Immediate Addressing S3F80JB ...
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... CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F80JB control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order ( detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual ...
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... E0H 225 E1H 226 E2H 227 E3H 228 E4H 229 E5H 230 E6H 231 E7H 232 E8H 233 E9H 234 EAH 235 EBH 236 ECH 237 EDH 238 EEH 239 EFH 240 F0H 241 F1H 242 F2H S3F80JB R/W (NOTE) R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (NOTE) R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
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... S3F80JB Register Name Counter A Control Register Counter A Data Register (High Byte) Counter A Data Register (Low Byte) Timer 1 Counter Register (High Byte) Timer 1 Counter Register (Low Byte) Timer 1 Data Register (High Byte) Timer 1 Data Register (Low Byte) Timer 1 Control Register STOP Control Register ...
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... Figure 4-1. Register Description Format Register address (Set ) Register address Register address (Hexadecimal) (Bank ) D5H Set1 Bank0 . R/W R/W R/W R/W RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one Bit number: MSB = Bit 7 LSB = Bit 0 S3F80JB ...
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... R Disable watchdog timer function Enable watchdog timer function f /4096 0 OSC f /1024 1 OSC f /128 0 OSC 1 Not used for S3F80JB. (1) No effect Clear the basic timer counter value No effect Clear both block frequency dividers CONTROL REGISTERS D3H Set1 Bank0 . R/W R/W R/W R/W (2) ...
Page 73
... Elapsed time for Low data value 1 Elapsed time for High data value 0 Elapsed time for combined Low and High data values 1 Not used for S3F80JB. Disable interrupt Enable interrupt Stop counter A Start counter A One-shot mode Repeating mode Flip-Flop Low level (T-FF = Low) ...
Page 74
... After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4. 2. These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid ...
Page 75
... Comparator Enable Bit Conversion Timer Control Bit External Reference Selection Bit 0 1 Not used for S3F80JB – .0 Reference Voltage Selection Bits Selected V NOTE: You can select the number of analog input pin for your purpose by setting the CMPSEL. 4 ...
Page 76
... S3F80JB CMPSEL — Comparator Input Selection Register Bit Identifier .7 Reset Value – Read/Write – Register addressing mode only Addressing Mode .7– .4 Not used for S3F80JB. .3 P2.7 Function Selection Bit P2.6 Function Selection Bit P2.5 Function Selection Bit P2.4 Function Selection Bit 0 1 NOTE bit of CMPSEL is set to “1”(Comparator input is selected), the port pin is operated as comparator input regardless of the P2CONH settings ...
Page 77
... Not used for S3F80JB NOTE: The EMT register is not used for S3F80JB, because an external peripheral interface is not implemented in the S3F80JB. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT values during normal operation may cause a system malfunction. ...
Page 78
... S3F80JB FLAGS — System Flags Register Bit Identifier .7 Reset Value x Read/Write R/W Register addressing mode only Addressing Mode .7 Carry Flag Bit ( Zero Flag Bit ( Sign Flag Bit ( Overflow Flag Bit ( Decimal Adjust Flag Bit (D) ...
Page 79
... Addressing Mode .7 – .4 Flash Memory Mode Selection Bits 0101 1010 0110 Others .3 – .1 Not used for S3F80JB .0 Flash Operation Start Bit (available for Erase and Hard Lock mode only NOTE: Hard Lock mode is one of the flash protection modes. Refer to page 15-18. 4-12 .6 ...
Page 80
... S3F80JB FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 – .0 Flash Memory Sector Address (High Byte) Note: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address ...
Page 81
... R/W R/W R/W Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) S3F80JB DDH Set1 Bank0 . R/W R/W R R/W ...
Page 82
... S3F80JB IPH — Instruction Pointer (High Byte) Bit Identifier .7 Reset Value R/W Read/Write Addressing Mode Register addressing mode only .7 – .1 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH) ...
Page 83
... Interrupt Group C Priority Control Bit Interrupt Subgroup B Priority Control Bit Interrupt Group B Priority Control Bit Interrupt Group A Priority Control Bit 0 1 NOTE: The S3F80JB interrupt structure uses eight levels: IRQ0-IRQ7. 4- R/W R/W R Group priority undefined > C > A ...
Page 84
... S3F80JB IRQ — Interrupt Request Register Bit Identifier .7 Reset Value 0 Read/Write R Register addressing mode only Addressing Mode .7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0 Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0 Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4 ...
Page 85
... Bit Identifier .7 Reset Value – Read/Write – Register addressing mode only Addressing Mode .7 – .1 Not used for S3F80JB. .0 LVD Flag (2.3V) Indicator Bit 0 1 NOTE: When LVD detects LVD_FLAG level (2.3V), LVDCON.0 flag bit is set automatically. When VDD is upper 2.3V, LVDCON.0 flag bit is cleared automatically. 4-18 .6 ...
Page 86
... S3F80JB P0CONH — Port 0 Control Register (High Byte) Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 and .6 P0.7/INT4 Mode Selection Bits and .4 P0.6/INT4 Mode Selection Bits and .2 P0.5/INT4 Mode Selection Bits and .0 P0 ...
Page 87
... C-MOS input mode; interrupt on rising and falling edges 0 Push-pull output mode 1 C-MOS input mode; interrupt on rising edges 0 C-MOS input mode; interrupt on falling edges 1 C-MOS input mode; interrupt on rising and falling edges 0 Push-pull output mode 1 C-MOS input mode; interrupt on rising edges S3F80JB E9H Set1 Bank0 . R/W R/W R/W .0 ...
Page 88
... S3F80JB P0INT — Port 0 External Interrupt Enable Register Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 P0.7 External Interrupt (INT4) Enable Bit P0.6 External Interrupt (INT4) Enable Bit P0.5 External Interrupt (INT4) Enable Bit P0.4 External Interrupt (INT4) Enable Bit ...
Page 89
... P0.3 external interrupt is pending (when read) No P0.2 external interrupt pending (when read) P0.2 external interrupt is pending (when read) No P0.1 external interrupt pending (when read) P0.1 external interrupt is pending (when read) No P0.0 external interrupt pending (when read) P0.0 external interrupt is pending (when read) S3F80JB F2H Set1 Bank0 . ...
Page 90
... S3F80JB P0PUR — Port 0 Pull-up Resistor Enable Register Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 P0.7 Pull-up Resistor Enable Bit P0.6 Pull-up Resistor Enable Bit P0.5 Pull-up Resistor Enable Bit P0.4 Pull-up Resistor Enable Bit P0.3 Pull-up Resistor Enable Bit ...
Page 91
... Push-pull output mode 1 C-MOS input with pull up mode 0 C-MOS input mode 1 Open-drain output mode 0 Push-pull output mode 1 C-MOS input with pull up mode 0 C-MOS input mode 1 Open-drain output mode 0 Push-pull output mode 1 C-MOS input with pull up mode S3F80JB EAH Set1 Bank0 . R/W R/W R R/W ...
Page 92
... S3F80JB P1CONL — Port 1 Control Register (Low Byte) Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 and .6 P1.3 Mode Selection Bits and .4 P1.2 Mode Selection Bits and .2 P1.1 Mode Selection Bits and .0 P1.0 Mode Selection Bits ...
Page 93
... C-MOS input mode; interrupt on rising and falling edges 0 Push-pull output mode 1 C-MOS input mode; interrupt on rising edges 0 C-MOS input mode; interrupt on falling edges 1 C-MOS input mode; interrupt on rising and falling edges 0 Push-pull output mode 1 C-MOS input mode; interrupt on rising edges S3F80JB ECH Set1 Bank0 . R/W R/W R ...
Page 94
... S3F80JB P2CONL — Port 2 Control Register (Low Byte) Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 and .6 P2.3/INT8 Mode Selection Bits and .4 P2.2/INT7 Mode Selection Bits and .2 P2.1/INT6 Mode Selection Bits and .0 P2 ...
Page 95
... R/W R/W R/W Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt S3F80JB E5H Set1 Bank0 . R/W R/W R R/W ...
Page 96
... S3F80JB P2PND — Port 2 External Interrupt Pending Register Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 P2.7 External Interrupt (INT9) Pending Flag Bit (see Note P2.6 External Interrupt (INT9) Pending Flag Bit P2.5 External Interrupt (INT9) Pending Flag Bit ...
Page 97
... Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor S3F80JB EEH Set1 Bank0 . R/W R/W R/W .0 ...
Page 98
... S3F80JB P3CON — Port 3 Control Register Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 and .6 Package Selection and Alternative Function Select Bits 0 Others .5 P3.1 Function Selection Bit and .3 P3.1 Mode Selection Bits Function Selection Bit for P3.0 & P3.3 ...
Page 99
... The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following Port 3 pin functions (bit 6 is not used for the S3F80JB: a. Port3, bit 7: carrier signal on (“1”) or off (“0”). b. Port3, bit 1,0: P3.1/REM/T0CK pin, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin. ...
Page 100
... P3.4 Mode Selection Bits and .1 Not used for S3F80JB. .0 Port 4 Control Register Selection Bit 0 1 NOTE: After CPU reset, P3.4 and P3.5 will be Open-drain output mode by the reset value of P345CON register at E1H, Set1, Bank1. P345CON will be initialized as “50h” to set P3.4 into the open-drain output mode after reset operation. ...
Page 101
... Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode S3F80JB F0H Set1 Bank0 . R/W R/W R/W ...
Page 102
... S3F80JB P4CONH — Port 4 Control Register (High Byte) Bit Identifier .7 Reset Value 1 Read/Write R/W Register addressing mode only Addressing Mode .7 and .6 P4.7 Mode Selection Bits and .4 P4.6 Mode Selection Bits and .2 P4.5 Mode Selection Bits and .0 P4.4 Mode Selection Bits ...
Page 103
... Push-pull output mode 1 C-MOS input with pull up mode 0 C-MOS input mode 1 Open-drain output mode 0 Push-pull output mode 1 C-MOS input with pull up mode 0 C-MOS input mode 1 Open-drain output mode 0 Push-pull output mode 1 C-MOS input with pull up mode S3F80JB E3H Set1 Bank1 . R/W R/W R R/W ...
Page 104
... Source Register Page Selection Bits 0 NOTE: In the S3F80JB microcontroller, a paged expansion of the internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to ‘0000B’ following a hardware reset. These values should not be changed curing normal operation ...
Page 105
... Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1,bank0, selecting the 8-byte working register slice C0H–C7H. .2 – .0 Not used for S3F80JB. RP1 — Register Pointer 1 Bit Identifier .7 ...
Page 106
... S3F80JB SPL — Stack Pointer (Low Byte) Bit Identifier .7 Reset Value x Read/Write R/W Register addressing mode only. Addressing Mode .7 – .0 Stack Pointer Address (Low Byte) The SP value is undefined following a reset. STOPCON — Stop Control Register Bit Identifier .7 Reset Value 0 Read/Write W Addressing Mode Register addressing mode only .7— ...
Page 107
... Global Interrupt Enable Bit 0 1 NOTES: 1. Because an external interface is not implemented for the S3F80JB, SYM.7 must always be "0". 2. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a “1” to this bit during normal operation, a system malfunction may occur. 3. ...
Page 108
... S3F80JB T0CON — Timer 0 Control Register Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 – .6 Timer 0 Input Clock Selection Bits and .4 Timer 0 Operating Mode Selection Bits Timer 0 Counter Clear Bit Timer 0 Overflow Interrupt Enable Bit (note) ...
Page 109
... Clear T1 counter, T1CNT (when write) Disable T1 overflow interrupt Enable T1 overflow interrupt Disable T1 match/capture interrupt Enable T1 match/capture interrupt No T1 match/capture interrupt pending (when read) Clear T1 match/capture interrupt pending condition (when write) T1 match/capture interrupt is pending (when read) No effect (when write) S3F80JB FAH Set1 Bank0 . R/W ...
Page 110
... S3F80JB T2CON — Timer 2 Control Register Bit Identifier .7 Reset Value 0 Read/Write R/W Register addressing mode only Addressing Mode .7 and .6 Timer 2 Input Clock Selection Bits and .4 Timer 2 Operating Mode Selection Bits Timer 2 Counter Clear Bit Timer 2 Overflow Interrupt Enable Bit (note) ...
Page 111
... S3C8/S3F8-series devices is always much smaller interrupt level has more than one vector address, the vector priorities are set in hardware. The S3F80JB uses eighteen vectors. Two vector addresses are shared by four interrupt sources. ...
Page 112
... The types differ in the number of vectors and interrupt sources assigned to each level (See Figure 5-1): Type 1: One level (IRQn) + one vector (V Type 2: One level (IRQn) + one vector (V Type 3: One level (IRQn) + multiple vectors (V In the S3F80JBmicrocontroller, all three interrupt types are implemented. Levels Type 1: Type 2: Type 3: NOTE: 5 one source (S ...
Page 113
... S3F80JB The S3F80JB microcontroller supports twenty-four interrupt sources. Sixteen of the interrupt sources have a corresponding interrupt vector address; the remaining eight interrupt sources share by two vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced ...
Page 114
... P2.1 external interrupt 0 D0H P2.0 external interrupt P2.7 external interrupt P2.6 external interrupt D8H P2.5 external interrupt P2.4 external interrupt 3 E6H P0.3 external interrupt 2 E4H P0.2 external interrupt 1 E2H P0.1 external interrupt 0 E0H P0.0 external interrupt P0.7 external interrupt P0.6 external interrupt E8H P0.5 external interrupt P0.4 external interrupt Figure 5-2. S3F80JB Interrupt Structure S3F80JB Reset/Clear H/W S/W H/W S/W H/W H/W S/W H/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W ...
Page 115
... S3F80JB INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80JB interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH (See Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses) ...
Page 116
... The priorities within a given level are fixed in hardware. 3. Reset (Basic timer overflow or POR) interrupt vector address can be changed by smart option (Refer to Table 15-3 or Figure 2-2). 5-6 Table 5-1. S3F80JB Interrupt Vectors Interrupt Source Basic timer overflow/POR Timer 0 match/capture Timer 0 overflow ...
Page 117
... IRQ0–IRQ7. IPR R/W Controls the relative processing priorities of the interrupt levels. The eight levels of the S3F80JB are organized into three groups and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7. IRQ ...
Page 118
... When writing the part of your application program that handles the interrupt processing, be sure to include the necessary register file address (register pointer) information nRESET R IRQ0-IRQ7 Interrupts 5-8 NOTE Q Interrupt Request Register (Read-only) Interrupt Priority Register Interrupt Mask Figure 5-4. Interrupt Function Diagram Polling Cycle Register Global Interrupt Control (EI SYM.0 manipulation) S3F80JB Vector Interrupt Cycle ...
Page 119
... S3F80JB PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3). Table 5-3. Vectored Interrupt Source Control and Data Registers Interrupt Source Timer 0 match/capture or Timer 0 overflow ...
Page 120
... EI and DI instructions for this purpose. MSB External Interface Tri-state Enable Bit Normal operation (Tri-state disabled High impedance (Tri-state enabled) NOTE: In case of S3F80JB, an external memory interface is not implemented. 5-10 System Mode Register (SYM) DEH, Set 1, Bank 0, R ...
Page 121
... S3F80JB INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to " ...
Page 122
... IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. — IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts. 5-12 IPR Group B22 B21 IRQ2 IRQ3 IRQ4 Figure 5-7. Interrupt Request Priority Groups IPR Group C21 C22 IRQ5 IRQ6 IRQ7 S3F80JB ...
Page 123
... S3F80JB MSB Group Priority Undefined > C > > B > > A > > A > > B > > C > Undefined Interrupt Priority Register (IPR) FEH, Set 1, Bank 0 , R/W ...
Page 124
... MSB 5-14 Interrupt Request Register (IRQ) DCH, Set 1, Bank 0 , Read-only . IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt Level Request Enable Bits Interrupt level is not pending 1 = Interrupt level is pending Figure 5-9. Interrupt Request Register (IRQ LSB IRQ0 IRQ1 IRQ2 S3F80JB ...
Page 125
... This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3F80JB interrupt structure, the timer 0 overflow interrupt (IRQ0), the timer 1 overflow interrupt (IRQ1), the timer 2 overflow interrupt (IRQ3), and the counter A interrupt (IRQ2) belong to this category of interrupts whose pending condition is cleared automatically by hardware ...
Page 126
... Branch to the interrupt vector to fetch the address of the service routine. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request. 5-16 S3F80JB ...
Page 127
... S3F80JB GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. ...
Page 128
... When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”). For the S3F80JB microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing. ...
Page 129
... S3F80JB 6 INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: — A full complement of 8-bit arithmetic and logic operations, including multiply and divide — ...
Page 130
... Load program memory with pre-decrement Load external data memory with pre-increment Load program memory with pre-increment Load word Pop from stack Pop user stack (decrementing) Pop user stack (incrementing) Push to stack Push user stack (decrementing) Push user stack (incrementing) S3F80JB Instruction ...
Page 131
... S3F80JB Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Arithmetic Instructions ADC dst,src ADD dst,src CP dst,src DA dst DEC dst DECW dst DIV dst,src INC dst INCW dst MULT dst,src SBC dst,src SUB dst,src Logic Instructions AND dst,src COM dst OR dst,src XOR dst,src ...
Page 132
... Decrement register and jump on non-zero Enter Exit Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Next Return Wait for interrupt Bit AND Bit compare Bit complement Bit reset Bit set Bit OR Bit XOR Test complement under mask Test under mask S3F80JB ...
Page 133
... S3F80JB Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SB0 SB1 SCF SRP src SRP0 src SRP1 src STOP Instruction ...
Page 134
... Flags register producing an unpredictable result. MSB Carry flag (C) Zero flag (Z) Sign flag (S) 6-6 System Flags Register (FLAGS) D5H, Set 1, Bank0 , R Overflow (V) Figure 6-1. System Flags Register (FLAGS LSB Bank address status flag (BA) First interrupt status flag (FIS) Half-carry flag (H) Decimal adjust flag (D) S3F80JB ...
Page 135
... S3F80JB FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. ...
Page 136
... Value is unaffected Value is undefined Table 6-3. Instruction Set Symbols Description Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register (D5H) Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode S3F80JB ...
Page 137
... S3F80JB Notation Description cc Condition code r Working register only rb Bit (b) of working register r0 Bit 0 (LSB) of working register rr Working register pair R Register or working register Rb Bit 'b' of register or working register RR Register pair or working register pair IA Indirect addressing mode Ir Indirect working register only IR Indirect register or indirect working register @Rn or @reg (reg = 0–255 0–15) ...
Page 138
... XOR XOR R2,R1 IR2,R1 R1,IM LDW LDW LDW RR2,RR1 IR2,RR1 RR1,IML CALL LD IA1 IR1, R2,R1 R2,IR1 R1,IM CALL LD CALL IRR1 IR2,R1 DA1 S3F80JB 7 BOR r0–Rb BCP r1.b, R2 BXOR r0–Rb BTJR r2.b, RA LDB r0–Rb BITC r1.b BAND r0–Rb BIT r1 LDC r1, Irr2, xL LDC r2, Irr2 ...
Page 139
... S3F80JB Table 6-5. Opcode Quick Reference (Continued) – r1,R2 r2,R1 ↓ ↓ ↓ r1,R2 r2,R1 OPCODE MAP LOWER NIBBLE (HEX DJNZ JR r1,RA cc,RA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ...
Page 140
... Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal S3F80JB Flags Set – – ...
Page 141
... S3F80JB INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: — Instruction name (mnemonic) — ...
Page 142
... R1. 6-14 Bytes 2 dst 3 src 3 → 14H 03H → 1BH 03H → Register 01H = 24H, register 02H = 03H → Register 01H = 2BH, register 02H = 03H → Register 01H = 32H S3F80JB Cycles Opcode Addr Mode (Hex) dst ...
Page 143
... S3F80JB ADD — Add ADD dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. ...
Page 144
... R1. 6-16 Bytes 2 dst 3 src 3 → 02H 03H → 02H 03H → Register 01H = 01H, register 02H = 03H → Register 01H = 00H, register 02H = 03H → Register 01H = 21H S3F80JB Cycles Opcode Addr Mode (Hex) dst ...
Page 145
... S3F80JB BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected ...
Page 146
... Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H). 6-18 Bytes src 3 → 07H, register 01H = 01H S3F80JB Cycles Opcode Addr Mode (Hex) dst 6 17 ...
Page 147
... S3F80JB BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. ...
Page 148
... LSB address value is one bit in length. Example: Given 07H: BITR R1.1 If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B). 6-20 → 05H Bytes Cycles Opcode (Hex S3F80JB Addr Mode dst rb ...
Page 149
... S3F80JB BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: opc dst | NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length ...
Page 150
... ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H. 6-22 Bytes src 3 dst 3 → 07H, register 01H = 03H → Register 01H = 07H 07H S3F80JB Cycles Opcode Addr Mode (Hex) dst ...
Page 151
... S3F80JB BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src( "0", then PC ← dst Operation: The specified bit within the source operand is tested "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; ...
Page 152
... Because "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 6-24 Bytes dst 3 S3F80JB Cycles Opcode Addr Mode (Hex) dst 10 ...
Page 153
... S3F80JB BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected ...
Page 154
... SP = 0000H (Memory locations 0000H = 1AH, 0001H = 4AH, where 4AH is the address that follows the instruction 0000H (0000H = 1AH, 0001H = 49H) → 0000H (0000H = 1AH, 0001H = 49H) Bytes Cycles Opcode (Hex S3F80JB Addr Mode dst DA IRR IA ...
Page 155
... S3F80JB CCF — Complement Carry Flag CCF C ← NOT C Operation: The carry flag (C) is complemented "1", the value of the carry flag is changed to logic zero "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. ...
Page 156
... In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 6-28 → Register 00H = 00H Register 01H = 02H, register 02H = 00H Bytes Cycles Opcode (Hex S3F80JB Addr Mode dst R IR ...
Page 157
... S3F80JB COM — Complement COM dst dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. ...
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... JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3. 6-30 dst src R1,R2 → Set the C and S flags R1,R2 UGE,SKIP R1 R3,R1 Bytes Cycles Opcode (Hex S3F80JB Addr Mode dst src ...
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... S3F80JB CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← Operation: Ir ← The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter ...
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... SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 6-32 Bytes dst 04H, PC jumps to SKIP location Cycles Opcode (Hex S3F80JB Addr Mode dst src r Ir ...
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... S3F80JB DA — Decimal Adjust DA dst dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not ...
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... C ← "0", H ← "0", Bits 4– bits 0– ← 3CH ; R1 ← 3CH + 3CH ← "0", H ← "0", Bits 4– bits 0– @R1 ← 31–0 ; S3F80JB ...
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... S3F80JB DEC — Decrement DEC dst dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. ...
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... A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example: LOOP: DECW RR0 6-36 → 12H 33H → Register 30H = 0FH, register 31H = 20H R2,R1 R2,R0 NZ,LOOP Bytes Cycles Opcode (Hex S3F80JB Addr Mode dst RR IR ...
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... S3F80JB DI — Disable Interrupts DI SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. ...
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... Bytes dst 3 → 03H 40H → 03H 20H → 03H 80H S3F80JB 9 –1; cleared otherwise. Cycles Opcode Addr Mode (Hex) dst 26/ 26/ 26/ ...
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... S3F80JB DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation ≠ ← dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to – ...
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... Given: SYM = 00H the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.) 6-40 Bytes Cycles Opcode (Hex S3F80JB ...
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... S3F80JB ENTER — Enter ENTER ← Operation: SP ← @SP ← IP ← PC ← IP This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two ...
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... 0022 SP 140 20 IPH IPL 22 Data Stack 6- Address IP Data PC PCL old 60 PCH 00 SP Exit 2F Memory 22 Bytes Cycles 1 14 (internal stack) 16 (internal stack) After Data 0052 Address 0060 60 Main 0022 Memory Data Stack S3F80JB Opcode (Hex) 2F Data ...
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... S3F80JB IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ external reset operation. Flags: No flags are affected. Format: opc Example: The instruction IDLE stops the CPU clock but not the system clock ...
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... In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. 6-44 dst → 1CH → Register 00H = 0DH → 1BH, register 01H = 10H Bytes Cycles Opcode (Hex S3F80JB Addr Mode dst ...
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... S3F80JB INCW — Increment Word INCW dst dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. ...
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... IPR register). 6-46 IRET (Fast) PC ↔ IP FLAGS ← FLAGS' FIS ← 0 Bytes 1 Bytes 1 0H FFH IRET 100H Interrupt Service Routine JP to FFH FFFFH S3F80JB Cycles Opcode (Hex) 10 (internal stack (internal stack) Cycles Opcode (Hex ...
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... S3F80JB JP — Jump JP cc,dst (Conditional) JP dst (Unconditional true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair ...
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... If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 6-48 Bytes dst 2 → 1FF7H S3F80JB Cycles Opcode Addr Mode (Hex) dst 6 ccB RA ...
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... S3F80JB LD — Load LD dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: dst | opc src | opc opc opc opc opc opc opc Bytes src dst dst | src ...
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... Register 00H = 20H, register 01H = 20H → Register 02H = 20H, register 00H = 01H → Register 00H = 0AH → Register 00H = 01H, register 01H = 10H → Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH 0AH Register 31H = 0AH 01H 0AH S3F80JB ...
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... S3F80JB LDB — Load Bit LDB dst,src.b LDB dst.b,src dst(0) ← src(b) Operation: or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected ...
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... S3F80JB Cycles Opcode Addr Mode (Hex) dst Irr [rr [rr [rr [rr ...
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... S3F80JB LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given 11H 34H 01H 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 LDE R0,@RR2 ...
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... R8 and RR6 is decremented by one ; R8 = 0CDH 10H 32H (RR6 ← RR6 – 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 ← RR6 – 0DDH 10H 32H S3F80JB Opcode Addr Mode (Hex) dst src ...
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... S3F80JB LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair ...
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... R0) is loaded into program memory location ; 2FFFH (3000H – 1H 77H 2FH 0FFH ; (RR6 ← RR6 – 77H (contents of R0) is loaded into external data memory ; location 2FFFH (3000H – 1H 77H 2FH 0FFH S3F80JB Opcode Addr Mode (Hex) dst src F2 ...
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... S3F80JB LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented ...
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... Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH → 03H 0FH, → Register 04H = 03H, register 05H = 0FH → 12H 34H → Register 02H = 0FH, register 03H = 0EDH S3F80JB Cycles Opcode Addr Mode (Hex) dst ...
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... S3F80JB MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. ...
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... The following diagram shows one example of how to use the NEXT instruction. Before Address Data IP 0043 Address 0120 120 6-60 Bytes 1 Address IP 0045 Data Data 0130 Address Address L 10 Address H Next Memory S3F80JB Cycles Opcode (Hex After Data Address Data 43 Address H 44 Address L 45 Address H 130 Routine Memory ...
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... S3F80JB NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: opc Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time ...
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... Bytes 2 dst 3 src 3 → 3FH 2AH → 37H 01H, register 01H = 37H → Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH → Register 00H = 0AH S3F80JB Cycles Opcode Addr Mode (Hex) dst ...
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... S3F80JB POP — Pop From Stack POP dst dst ← @SP Operation: SP ← The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: opc dst Examples: Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, ...
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... The user stack pointer is then decremented by one, leaving the value 41H. 6-64 Bytes dst 3 → Register 00H = 41H, register 02H = 6FH, register 42H = 6FH S3F80JB Cycles Opcode Addr Mode (Hex) dst 8 92 ...
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... S3F80JB POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented ...
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... Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH → Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH S3F80JB Opcode Addr Mode (Hex) dst ...
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... S3F80JB PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer ...
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... The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer. 6-68 Bytes src 3 Register 00H = 04H, register 01H = 05H, register 04H = 05H S3F80JB Cycles Opcode Addr Mode (Hex) dst 8 83 ...
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... S3F80JB RCF — Reset Carry Flag RCF RCF C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: opc Example: Given "1" or "0": The instruction RCF clears the carry flag (C) to logic zero. ...
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... The stack pointer then pops the value in location 00FEH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH. 6-70 Bytes 101AH 00FEH S3F80JB Cycles Opcode (Hex) 8 (internal stack (internal stack) ...
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... S3F80JB RL — Rotate Left RL dst C ← dst (7) Operation: dst (0) ← dst (7) dst ( ← dst (n 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. ...
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... The MSB of register 00H resets the carry flag to "1" and sets the overflow flag. 6- Bytes 2 → Register 00H = 54H "1" → Register 01H = 02H, register 02H = 2EH "0" S3F80JB Cycles Opcode Addr Mode (Hex) dst ...