MC9S08GB60 Freescale Semiconductor, Inc, MC9S08GB60 Datasheet
MC9S08GB60
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... MC9S08GB60 MC9S08GB32 MC9S08GT60 MC9S08GT32 MC9S08GT16 Data Sheet HCS08 Microcontrollers MC9S08GB60/D Rev. 2.3 12/2004 freescale.com ...
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... MC9S08GB/GT Data Sheet Covers: MC9S08GB60 MC9S08GB32 MC9S08GT60 MC9S08GT32 MC9S08GT16 MC9S08GB60 Rev. 2.3 12/2004 ...
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... Minor changes to Clarifications in 2.3 12/01/2004 and Status package (see This product incorporates SuperFlash Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2004. All rights reserved. 4 Description of Changes values to Electricals, appendix A DD Table A-9 and added a figure ...
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List of Chapters Chapter 1 Introduction.............................................................................. 17 Chapter 2 Pins and Connections ............................................................. 23 Chapter 3 Modes of Operation ................................................................. 33 Chapter 4 Memory ..................................................................................... 39 Chapter 5 Resets, Interrupts, and System Configuration ..................... 61 Chapter 6 Parallel Input/Output ............................................................... ...
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Section Number 1.1 Overview .........................................................................................................................................17 1.2 Features ...........................................................................................................................................17 1.2.1 Standard Features of the HCS08 Family .........................................................................17 1.2.2 Features of MC9S08GB/GT Series of MCUs .................................................................17 1.2.3 Devices in the MC9S08GB/GT Series ............................................................................18 1.3 MCU Block Diagrams .....................................................................................................................19 1.4 System Clock Distribution ...
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Section Number 4.1 MC9S08GB/GT Memory Map .......................................................................................................39 4.1.1 Reset and Interrupt Vector Assignments ..........................................................................39 4.2 Register Addresses and Bit Assignments ........................................................................................41 4.3 RAM ................................................................................................................................................46 4.4 FLASH ............................................................................................................................................46 4.4.1 Features ............................................................................................................................47 4.4.2 Program and Erase Times ................................................................................................47 4.4.3 Program and Erase ...
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Section Number 5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................68 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................68 5.8.2 System Reset Status Register (SRS) ................................................................................69 5.8.3 System Background Debug Force Reset Register (SBDFR) ...........................................71 5.8.4 ...
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Section Number Internal Clock Generator (ICG) Module 7.1 Introduction .....................................................................................................................................99 7.1.1 Features ..........................................................................................................................100 7.1.2 Modes of Operation .......................................................................................................101 7.2 External Signal Description ..........................................................................................................101 7.2.1 Overview ........................................................................................................................101 7.2.2 Detailed Signal Descriptions .........................................................................................102 7.2.2.1 EXTAL— External Reference Clock / Oscillator Input ...............................102 ...
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Section Number 8.1 Introduction ...................................................................................................................................125 8.2 Features .........................................................................................................................................126 8.3 Programmer’s Model and CPU Registers .....................................................................................126 8.3.1 Accumulator (A) ............................................................................................................127 8.3.2 Index Register (H:X) .....................................................................................................127 8.3.3 Stack Pointer (SP) ..........................................................................................................128 8.3.4 Program Counter (PC) ...................................................................................................128 8.3.5 Condition Code Register (CCR) ....................................................................................128 ...
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Section Number 10.1 Introduction ...................................................................................................................................151 10.2 Features .........................................................................................................................................151 10.3 TPM Block Diagram .....................................................................................................................153 10.4 Pin Descriptions ............................................................................................................................154 10.4.1 External TPM Clock Sources ........................................................................................154 10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................154 10.5 Functional Description ..................................................................................................................154 10.5.1 Counter ..........................................................................................................................155 10.5.2 ...
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Section Number 11.8 Additional SCI Functions ..............................................................................................................176 11.8.1 8- and 9-Bit Data Modes ................................................................................................176 11.9 Stop Mode Operation ....................................................................................................................176 11.9.1 Loop Mode .....................................................................................................................177 11.9.2 Single-Wire Operation ...................................................................................................177 11.10 SCI Registers and Control Bits .....................................................................................................177 11.10.1 SCI x Baud Rate Registers ...
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Section Number Inter-Integrated Circuit (IIC) Module 13.1 Introduction ...................................................................................................................................205 13.1.1 Features ..........................................................................................................................205 13.1.2 Modes of Operation .......................................................................................................205 13.1.3 Block Diagram ...............................................................................................................206 13.1.4 Detailed Signal Descriptions .........................................................................................206 13.1.4.1 SCL1 — Serial Clock Line ...........................................................................206 13.1.4.2 SDA1 — Serial Data Line ............................................................................206 ...
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Section Number 14.2.1.2 ATD Reference Pins — V 14.2.1.3 ATD Supply Pins — V 14.3 Functional Description ..................................................................................................................223 14.3.1 Mode Control .................................................................................................................223 14.3.2 Sample and Hold ............................................................................................................224 14.3.3 Analog Input Multiplexer ..............................................................................................226 14.3.4 ATD Module Accuracy Definitions ...............................................................................226 14.4 Resets ...
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Section Number 15.5.3.5 Debug FIFO High Register (DBGFH) ..........................................................253 15.5.3.6 Debug FIFO Low Register (DBGFL) ...........................................................253 15.5.3.7 Debug Control Register (DBGC) ..................................................................254 15.5.3.8 Debug Trigger Register (DBGT) ..................................................................255 15.5.3.9 Debug Status Register (DBGS) .....................................................................256 A.1 Introduction ...................................................................................................................................259 A.2 Absolute Maximum ...
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Chapter 1 Introduction 1.1 Overview The MC9S08GB/GT are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, ...
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... MC9S08GTxx 1.2.3 Devices in the MC9S08GB/GT Series Table 1-1 lists the devices available in the MC9S08GB/GT series and summarizes the differences among them. Table 1-1. Devices in the MC9S08GB/GT Series Device FLASH MC9S08GB60 60K MC9S08GB32 32K MC9S08GT60 60K MC9S08GT32 32K MC9S08GT16 ...
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MCU Block Diagrams These block diagrams show the structure of the MC9S08GB/GT MCUs. HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD ...
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Chapter 1 Introduction HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD USER FLASH (GT60 = 61,268 BYTES) (GT32 = 32,768 BYTES) (GT16 ...
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Table 1-2 lists the functional versions of the on-chip modules. Serial Communications Interface (SCI) 1.4 System Clock Distribution SYSTEM CONTROL LOGIC ICGERCLK FFE ÷ 2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT ÷ 2 ICGLCLK* CPU * ICGLCLK is the alternate ...
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Chapter 1 Introduction • FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK. Otherwise ...
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Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment 64 63 RESET 1 PTG7 ...
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Chapter 2 Pins and Connections RESET 1 PTC0/TxD2 2 PTC1/RxD2 3 PTC2/SDA1 4 PTC3/SCL1 5 PTC4 6 PTC5 7 PTC6 8 PTC7 9 PTE0/TxD1 10 11 PTE1/RxD1 12 IRQ Figure 2-2. MC9S08GTxx in 48-Pin QFN Package 24 MC9S08GB/GT Data Sheet, ...
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RESET 1 PTC0/TxD2 PTC1/RxD2 PTC2/SDA1 PTC3/SCL1 PTC4 PTC5 PTC6 PTE0/TxD1 PTE1/RxD1 IRQ 11 Figure 2-3. MC9S08GTxx in 44-Pin QFP Package Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Device Pin Assignment PTA1/KBI1P1 ...
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... PTE4/MOSI1 PTE5/SPSCK1 PTD0/TPM1CH0 Figure 2-4. MC9S08GTxx in 42-Pin SDIP Package 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08GB60 application systems. MC9S08GTxx connections will be similar except for the number of I/O pins available. A more detailed discussion of system connections follows DDAD ...
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V SYSTEM DD POWER + + C C BLK µF NOTE BACKGROUND HEADER V DD OPTIONAL ASYNCHRONOUS MANUAL INTERRUPT RESET INPUT PTG0/BKDG/MS PTG1/XTAL PTG2/EXTAL NOTES: PTG3 1. Not required if PTG4 ...
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Chapter 2 Pins and Connections 2.3.1 Power V and V are the primary power supply pins for the MCU. This voltage source supplies power to all DD SS I/O buffer circuitry and to an internal voltage regulator. The internal voltage ...
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MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is ...
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Chapter 2 Pins and Connections To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins ...
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IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. 2.3.6 Signal Properties Summary Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by ...
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Chapter 2 Pins and Connections Pin High Current Dir Name Pin PTC4 I/O Y PTC5 I/O Y PTC6 I/O Y PTC7 I/O Y PTD0/TPM1CH0 I/O N PTD1/TPM1CH1 I/O N PTD2/TPM1CH2 I/O N PTD3/TPM2CH0 I/O N PTD4/TPM2CH1 I/O N PTD5/TPM2CH2 I/O ...
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Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08GB/GT are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 Features • Active ...
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Chapter 3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is ...
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Table 3-1 summarizes the behavior of the MCU in each of the stop modes. CPU, Digital Mode PDC PPDC Peripherals, FLASH Stop1 1 0 Off Stop2 1 1 Off Stop3 0 Don’t Standby care 1 Either ATD stop mode or ...
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Chapter 3 Modes of Operation Exit from stop2 is performed by asserting either of the wake-up pins: RESET or IRQ RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of ...
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If the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available ...
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Chapter 3 Modes of Operation I/O Pins • All I/O pin states remain unchanged when the MCU enters stop3 mode. • If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop. ...
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... FLASH 59348 BYTES $FFFF MC9S08GB60/MC9S08GT60 4.1.1 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08GB/GT. For more details about ...
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Chapter 4 Memory resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Interrupts, and System Configuration.” Address (High/Low) $FFC0:FFC1 $FFCA:FFCB $FFCC:FFCD $FFCE:FFCF $FFD0:FFD1 $FFD2:FFD3 $FFD4:FFD5 $FFD6:FFD7 $FFD8:FFD9 $FFDA:FFDB $FFDC:FFDD $FFDE:FFDF $FFE0:FFE1 $FFE2:FFE3 $FFE4:FFE5 $FFE6:FFE7 $FFE8:FFE9 $FFEA:FFEB $FFEC:FFED $FFEE:FFEF ...
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Register Addresses and Bit Assignments The registers in the MC9S08GB/GT are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode ...
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Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet Address Register Name Bit 7 $0000 PTAD PTAD7 $0001 PTAPE PTAPE7 $0002 PTASE PTASE7 $0003 PTADD PTADD7 $0004 PTBD PTBD7 $0005 PTBPE PTBPE7 $0006 PTBSE PTBSE7 $0007 PTBDD ...
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Table 4-2. Direct-Page Register Summary (Sheet Address Register Name Bit 7 $0028 SPI1C1 SPIE $0029 SPI1C2 0 $002A SPI1BR 0 $002B SPI1S SPRF $002C Reserved 0 $002D SPI1D Bit 7 $002E Reserved 0 $002F Reserved 0 $0030 ...
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Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet Address Register Name Bit 7 $004F Reserved 0 $0050 ATD1C ATDPU $0051 ATD1SC CCF $0052 ATD1RH Bit 7 $0053 ATD1RL Bit 7 $0054 ATD1PE ATDPE7 $0055– — Reserved ...
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High-page registers, shown in Table so they have been located outside the direct addressable memory space, starting at $1800. Address Register Name Bit 7 $1800 SRS POR $1801 SBDFR 0 $1802 SOPT COPE $1803 – — Reserved $1805 — $1806 ...
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Chapter 4 Memory Address Register Name Bit 7 $FFB0 – NVBACKKEY $FFB7 $FFB8 – Reserved — $FFBC — $FFBD NVPROT FPOPEN 1 $FFBE Reserved — $FFBF NVOPT KEYEN 1 This location is used to store the factory trim value for ...
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... Features Features of the FLASH memory include: • FLASH Size — MC9S08GB60/MC9S08GT60 — 61268 bytes (120 pages of 512 bytes each) — MC9S08GB32/MC9S08GT32— 32768 bytes (64 pages of 512 bytes each) — MC9S08GT16 — 16384 bytes (32 pages of 512 bytes each) • Single power supply program and erase • ...
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Chapter 4 Memory 4.4.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: ...
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Figure 4-2. FLASH Program and Erase Flowchart 4.4.4 Burst Program Execution The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the ...
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Chapter 4 Memory program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the ...
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Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register • Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the ...
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Chapter 4 Memory 4.4.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled ...
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FLASH locations. If KEYEN secure user program can temporarily disengage security by: 1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret ...
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Chapter 4 Memory 4.6.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or ...
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PRDIV8 f Bus (Binary) 20 MHz 1 10 MHz 0 8 MHz 0 4 MHz 0 2 MHz 0 1 MHz 0 200 kHz 0 150 kHz 0 4.6.2 FLASH Options Register (FOPT and NVOPT) During reset, the contents of ...
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Chapter 4 Memory SEC01:SEC00 — Security State Code This 2-bit field determines the security state of the MCU as shown in secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the ...
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Bit 7 Read: FPOPEN Write: 1 Reset: 1 Background commands can be used to change the contents of these bits in FPROT. Figure 4-7. FLASH Protection Register (FPROT) FPOPEN — Open Unprotected FLASH for Program/Erase 1 = Any FLASH location, ...
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Chapter 4 Memory 4.6.5 FLASH Status Register (FSTAT) Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these ...
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FBLANK — FLASH Verified as All Blank (Erased) Flag FBLANK is set automatically at the conclusion of a blank check command if the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a ...
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Chapter 4 Memory 60 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...
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Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08GB/GT. Some interrupt sources from peripheral modules are discussed in greater detail within ...
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Chapter 5 Resets, Interrupts, and System Configuration Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) ...
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When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction and consists of: • Saving the CPU registers on the ...
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Chapter 5 Resets, Interrupts, and System Configuration UNSTACKING ORDER STACKING ORDER When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of ...
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The voltage measured on the pulled up IRQ pin may be as low The internal gates connected to this pin are pulled all the way to V other pins with enabled pullup resistors will have an unloaded ...
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Chapter 5 Resets, Interrupts, and System Configuration Vector Vector Address Priority Number (High/Low) 26 $FFC0/FFC1 through through Lower 31 $FFCA/FFCB 25 $FFCC/FFCD 24 $FFCE/FFCF 23 $FFD0/FFD1 22 $FFD2/FFD3 21 $FFD4/FFD5 20 $FFD6/FFD7 19 $FFD8/FFD9 18 $FFDA/FFDB 17 $FFDC/FFDD 16 $FFDE/FFDF ...
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Low-Voltage Detect (LVD) System The MC9S08GB/GT includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD ...
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Chapter 5 Resets, Interrupts, and System Configuration When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and configured for low bandwidth operation (RANGE = 0). The SRTISC register includes a read-only status ...
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IRQPE — IRQ Pin Enable This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used as an interrupt request. Also, when this bit is set, either an internal pull-up or ...
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Chapter 5 Resets, Interrupts, and System Configuration Bit 7 Read: POR Write: Power-on reset: 1 Low-voltage reset: U Any other reset Unaffected by reset 1 Any of these reset sources that are active at the time of ...
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LVD — Low Voltage Detect If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop. To ...
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Chapter 5 Resets, Interrupts, and System Configuration COPE — COP Watchdog Enable This write-once bit defaults to 1 after reset COP watchdog timer enabled (force reset on timeout COP watchdog timer disabled. COPT — COP Watchdog ...
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ID[11:0] — Part Identification Number Each derivative in the HCS08 Family has a unique identification number. The MC9S08GB/GT is hard coded to the value $002. 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status ...
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Chapter 5 Resets, Interrupts, and System Configuration RTIS2:RTIS1:RTIS0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 1 See Table A- Appendix A, “Electrical RTI based on the external clock source, resonator, or crystal selected by ...
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LVDRE — Low-Voltage Detect Reset Enable This read/write bit enables LVDF events to generate a hardware reset (provided LVDE = 1 Force an MCU reset when LVDF = LVDF does not generate hardware resets. LVDSE ...
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Chapter 5 Resets, Interrupts, and System Configuration LVDV — Low-Voltage Detect Voltage Select The LVDV bit selects the LVD trip point voltage ( High trip point selected ( Low trip point selected (V LVWV — Low-Voltage ...
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Chapter 6 Parallel Input/Output 6.1 Introduction This section explains software controls related to parallel input/output (I/O). The MC9S08GBxx has seven I/O ports which include a total of 56 general-purpose I/O pins (one of these pins is output only). The MC9S08GTxx ...
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Chapter 6 Parallel Input/Output HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD USER FLASH (GB60 = 61,268 BYTES) (GB32 = 32,768 BYTES) ...
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Features Parallel I/O features, depending on package choice, include: • A total of 56 general-purpose I/O pins in seven ports (PTG0 is output only) • High-current drivers on port C and port F pins • Hysteresis input buffers • ...
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Chapter 6 Parallel Input/Output Port A can be configured to be keyboard interrupt input pins. Refer to (KBI) Module,” for more information about using port A pins as keyboard interrupts pins. 6.3.2 Port B and Analog to Digital Converter Inputs ...
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Port D, TPM1 and TPM2 Port D Bit 7 PTD7/ MCU Pin: TPM2CH4 Port 8-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O. When the TPM1 or TPM2 modules are enabled ...
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Chapter 6 Parallel Input/Output 6.3.6 Port F and High-Current Drivers Port F Bit 7 MCU Pin: PTF7 Port 8-bit port general-purpose I/O that is not shared with any peripheral module. Port F has high current output drivers. ...
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Reads of the data register return the pin value (if PTxDDn = 0) or the contents of the port data register (if PTxDDn = 1). Writes to the port data register are latched into the port register whether the pin ...
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Chapter 6 Parallel Input/Output 6.5 Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • When the MCU enters stop1 ...
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PTAD Bit 7 Read: PTAD7 Write: Reset: 0 PTAPE Read: PTAPE7 Write: Reset: 0 PTASE Read: PTASE7 Write: Reset: 0 PTADD Read: PTADD7 Write: Reset: 0 PTADn — Port A Data Register Bit 0–7) For port A ...
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Chapter 6 Parallel Input/Output PTASEn — Slew Rate Control Enable for Port A Bit 0–7) For port A pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port ...
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PTBDn — Port B Data Register Bit 0–7) For port B pins that are inputs, reads return the logic level on the pin. For port B pins that are configured as outputs, reads return the last value ...
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Chapter 6 Parallel Input/Output PTCD Bit 7 Read: PTCD7 Write: Reset: 0 PTCPE Read: PTCPE7 Write: Reset: 0 PTCSE Read: PTCSE7 Write: Reset: 0 PTCDD Read: PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 Write: Reset: 0 PTCDn — Port ...
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PTCDDn — Data Direction for Port C Bit 0–7) These read/write bits control the direction of port C pins and what is read for PTCD reads Output driver enabled for port C bit n and ...
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Chapter 6 Parallel Input/Output PTDDn — Port D Data Register Bit 0–7) For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are configured as outputs, reads ...
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PTED Bit 7 Read: PTED7 Write: Reset: 0 PTEPE Read: PTEPE7 Write: Reset: 0 PTESE Read: PTESE7 Write: Reset: 0 PTEDD Read: PTEDD7 Write: Reset: 0 PTEDn — Port E Data Register Bit 0–7) For port E ...
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Chapter 6 Parallel Input/Output PTEDDn — Data Direction for Port E Bit 0–7) These read/write bits control the direction of port E pins and what is read for PTED reads Output driver enabled for port ...
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PTFPEn — Pullup Enable for Port F Bit 0–7) For port F pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. For port F pins that are configured as outputs, these ...
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Chapter 6 Parallel Input/Output PTGD Bit 7 Read: PTGD7 Write: Reset: 0 PTGPE Read: PTGPE7 Write: Reset: 0 PTGSE Read: PTGSE7 Write: Reset: 0 PTGDD Read: PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 Write: Reset: 0 PTGDn — Port ...
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PTGDDn — Data Direction for Port G Bit 0–7) These read/write bits control the direction of port G pins and what is read for PTGD reads Output driver enabled for port G bit n and ...
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Chapter 6 Parallel Input/Output 96 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...
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Chapter 7 Internal Clock Generator (ICG) Module The MC9S08GB/GT microcontroller provides one internal clock generation (ICG) module to create the system bus frequency. All functions described in this section are available on the MC9S08GB/GT microcontroller. The EXTAL and XTAL pins ...
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Chapter 7 Internal Clock Generator (ICG) Module HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD USER FLASH (GB60 = 61,268 BYTES) (GB32 ...
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Introduction Figure 7 top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list. EXTAL OSCILLATOR (OSC) WITH EXTERNAL REF SELECT XTAL V DDA ...
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Internal Clock Generator (ICG) Module Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or • external clock source and multiplies higher frequency. Status bits provide information when the circuit has achieved lock and ...
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Modes of Operation This is a high-level description only. Detailed descriptions of operating modes are contained in Section 7.3, “Functional Description." • Mode 1 — Off The output clock, ICGOUT, is static. This mode may be entered when the ...
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Internal Clock Generator (ICG) Module 7.2.2 Detailed Signal Descriptions This section describes each pin signal in detail. 7.2.2.1 EXTAL— External Reference Clock / Oscillator Input If the first write to the ICG control register 1 selected FLL engaged external or ...
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Figure 7-5. External Frequency Reference Connection 7.3 Functional Description This section provides a functional description of each of the five operating modes of the ICG. Also covered are the loss of clock and loss of lock errors and requirements for ...
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Internal Clock Generator (ICG) Module 7.3.1.3 Stop/Off Mode Recovery Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system clock feed resumes. If FEE is selected, the ICG will source ...
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CLKST REFERENCE DIVIDER (/7) RANGE MFD SUBTRACTOR OVERFLOW COUNTER ENABLE RANGE LOCK AND LOSS OF CLOCK DETECTOR DCOS LOCK LOLS Figure 7-6. Detailed Frequency-Locked Loop Block Diagram 7.3.3 FLL Engaged, Internal Clock (FEI) Mode FLL engaged internal (FEI) is entered ...
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Internal Clock Generator (ICG) Module The ICG will remain in this state while the count error (∆n) is greater than the maximum n the minimum required by the lock detector to detect the lock condition. lock In ...
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The ICG will remain in this state while the count error (∆n) is greater than the maximum n the minimum required by the lock detector to detect the lock condition. lock In this state, the pulse counter, ...
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Internal Clock Generator (ICG) Module ICGS1 then writing 1 to ICGIF (LOCRE = 0 loss-of-clock induced reset (LOCRE = 1 any MCU reset. If the ICG is in FEE, a loss of reference clock causes ...
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Actual Desired Mode Mode Range (f (CLKST) (CLKS) Off X (XX) Off (XX) FBE X (10) SCM X (00) FEI 0 (01) SCM (00) FBE X (10) FEE X (11) FEI 0 (01) FEI (01) FEE X (11) FBE X ...
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Internal Clock Generator (ICG) Module When the ICG is in either FEI or SCM mode, XCLK is turned off. Any peripherals which can use XCLK as a clock source must not do so when the ICG is in FEI or ...
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Table 7-5. ICGOUT Frequency Calculation Options Clock Scheme SCM — self-clocked mode (FLL bypassed internal) FBE — FLL bypassed external FEI — FLL engaged internal FEE — FLL engaged external f 1. Ensure that , which is equal to ICGDCLK ...
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Internal Clock Generator (ICG) Module 7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38-MHz to ...
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RECOVERY FROM RESET, STOP1, OR STOP2 INITIALIZE ICG ICG1 = $38 ICG2 = $00 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Figure 7-8. ICG Initialization for FEE in Example #1 7.4.3 Example #2: External Crystal = 4 ...
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Internal Clock Generator (ICG) Module ICGC2 = $30 (%00110000) Bit 7 LOLRE 0 Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10 Bit 3 LOCRE 0 Bit 2:0 RFD 000 Sets the RFD division factor to ÷1 ICGS1 ...
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The clock scheme will be FLL engaged, internal (FEI ICGOUT Solving for gives 10.8 MHz /(243/7 kHz * 64 can choose and ...
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Internal Clock Generator (ICG) Module RECOVERY FROM RESET, STOP1, OR STOP2 INITIALIZE ICG ICG1 = $28 ICG2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? YES CONTINUE Figure 7-10. ICG Initialization and Stop Recovery for Example #3 7.4.5 Example ...
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Initial conditions: 1) Clock supplied from ATE has 500 µs duty period 2) ICG configured for internal reference with 4 MHz bus COUNT < EXPECTED = 500 (RUNNING TOO SLOW) ICGTRM = ICGTRM - 128 / (2**n) (DECREASING ICGTRM INCREASES ...
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Internal Clock Generator (ICG) Module 7.5.1 ICG Control Register 1 (ICGC1) Bit 7 Read: 0 Write: Reset This bit is reserved for Freescale Semiconductor internal use only. Any write operations to this register should write ...
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OSCSTEN — Enable Oscillator in Off Mode The OSCSTEN bit controls whether or not the oscillator circuit remains enabled when the ICG enters off mode Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST ...
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Internal Clock Generator (ICG) Module LOCRE — Loss of Clock Reset Enable The LOCRE bit determines how the system handles a loss of clock condition Generate a reset request on loss of clock Generate an interrupt ...
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CLKST[1:0] REFST — Reference Clock Status The REFST bit indicates which clock reference is currently selected by the Reference Select circuit Crystal/Resonator selected External Clock selected. LOLS — FLL Loss of Lock Status The LOLS bit ...
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Internal Clock Generator (ICG) Module ICGIF — ICG Interrupt Flag The ICGIF read/write flag is set when an ICG interrupt request is pending cleared by a reset or by reading the ICG status register when ICGIF is set ...
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Bit 7 Read: Write: Reset: 1 Figure 7-18. ICG Lower Filter Register (ICGFLTL) The filter registers show the filter value (FLT). FLT — Filter Value The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT ...
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Internal Clock Generator (ICG) Module 124 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...
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Chapter 8 Central Processor Unit (CPU) 8.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, ...
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Central Processor Unit (CPU) 8.2 Features Features of the HCS08 CPU include: • Object code fully upward-compatible with M68HC05 and M68HC08 Families • All registers and memory are mapped to a single 64-Kbyte address space • 16-bit stack pointer (any ...
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H INDEX REGISTER (HIGH CONDITION CODE REGISTER 8.3.1 Accumulator (A) The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU) is connected to the accumulator and the ALU results are often ...
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Central Processor Unit (CPU) 8.3.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and ...
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V — Two’s Complement Overflow Flag The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag Overflow overflow H — ...
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Central Processor Unit (CPU) 8.4 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a ...
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Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.4.6 Indexed Addressing Mode Indexed addressing mode has ...
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Central Processor Unit (CPU) 8.4.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete ...
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For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register ...
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Central Processor Unit (CPU) 8.5.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter ...
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Condition code register (CCR) bits V = Two’s complement overflow indicator, bit Half carry, bit Interrupt mask, bit Negative indicator, bit Zero indicator, bit Carry/borrow, ...
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Central Processor Unit (CPU) rel — Any label or expression that refers to an address that is within –128 to +127 locations from the next address after the last byte of object code for the current instruction. The assembler will ...
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Table 8-1. HCS08 Instruction Set Summary (Sheet Source Operation Form ASL opr8a ASLA ASLX Arithmetic Shift Left ASL oprx8,X (Same as LSL) ASL ,X ASL oprx8,SP ASR opr8a ASRA ASRX Arithmetic Shift Right ASR oprx8,X ASR ,X ...
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Central Processor Unit (CPU) Table 8-1. HCS08 Instruction Set Summary (Sheet Source Operation Form BMI rel Branch if Minus Branch if Interrupt Mask BMS rel Set BNE rel Branch if Not Equal BPL rel Branch if Plus ...
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Table 8-1. HCS08 Instruction Set Summary (Sheet Source Operation Form COM opr8a COMA COMX Complement COM oprx8,X (One’s Complement) COM ,X COM oprx8,SP CPHX opr16a CPHX #opr16i Compare Index Register CPHX opr8a (H:X) with Memory CPHX oprx8,SP ...
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Central Processor Unit (CPU) Table 8-1. HCS08 Instruction Set Summary (Sheet Source Operation Form LDA #opr8i LDA opr8a LDA opr16a LDA oprx16,X Load Accumulator from LDA oprx8,X Memory LDA ,X LDA oprx16,SP LDA oprx8,SP LDHX #opr16i LDHX ...
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Table 8-1. HCS08 Instruction Set Summary (Sheet Source Operation Form Pull Accumulator from PULA Stack Pull H (Index Register PULH High) from Stack Pull X (Index Register PULX Low) from Stack ROL opr8a ROLA ROLX Rotate Left ...
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Central Processor Unit (CPU) Table 8-1. HCS08 Instruction Set Summary (Sheet Source Operation Form SUB #opr8i SUB opr8a SUB opr16a SUB oprx16,X Subtract SUB oprx8,X SUB ,X SUB oprx16,SP SUB oprx8,SP SWI Software Interrupt Transfer Accumulator to ...
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Bit-Manipulation Branch BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH BRCLR0 BCLR0 BRN CBEQ CBEQA ...
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Central Processor Unit (CPU) Bit-Manipulation Branch INH Inherent REL Relative IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR ...
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Chapter 9 Keyboard Interrupt (KBI) Module 9.1 Introduction The MC9S08GB/GT has one KBI module with eight keyboard interrupt inputs that share port A pins. See Chapter 2, “Pins and Connections” for more information about the logic and hardware aspects of ...
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Chapter 9 Keyboard Interrupt (KBI) Module HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD USER FLASH (GB60 = 61,268 BYTES) (GB32 = ...
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KBI Block Diagram Figure 9-3 shows the block diagram for a KBI module. KBI1P0 KBIPE0 KBI1P3 KBIPE3 1 0 KBI1P4 S KBIPE4 KBEDG4 1 KBI1Pn 0 S KBIPEn KBEDGn The KBI module allows up to eight pins to act ...
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Keyboard Interrupt (KBI) Module A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. The KBIMOD control bit can be set to ...
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KBEDGn — Keyboard Edge Select for KBI Port Bit 7–4) Each of these read/write bits selects the polarity of the edges and/or levels that are recognized as trigger events on the corresponding KBI port pin when it ...
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Keyboard Interrupt (KBI) Module 9.5.2 KBI Pin Enable Register (KBI1PE) Bit 7 Read: KBIPE7 Write: Reset: Figure 9-5. KBI Pin Enable Register (KBI1PE) KBIPEn — Keyboard Pin Enable for KBI Port Bit 7–0) Each of these read/write ...
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... ICG in either FEI or SCM mode will result in the TPM being non-functional. 10.2 Features The timer system in the MC9S08GB60 includes a 3-channel TPM1 and a separate 5-channel TPM2; the timer system in the MC9S08GB32 includes two 2-channel modules, TPM1 and TPM2. Timer system features include: • ...
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Chapter 10 Timer/PWM (TPM) Module HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES RTI COP 2, 3 IRQ LVD USER FLASH (GB60 = 61,268 BYTES) (GB32 = 32,768 ...
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TPM Block Diagram The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example and n is the channel number (for example, 0–4). The TPM shares its I/O pins ...
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Timer/PWM (TPM) Module counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values $0000 ...
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TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of ...
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Timer/PWM (TPM) Module Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are captured into a ...
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The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible. As Figure 10-3 shows, the output compare value in the TPM ...
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Timer/PWM (TPM) Module generation of 100 percent duty cycle is not necessary). This is not a significant limitation because the resulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL = $0000 is a special case that should not ...
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TPM Interrupts The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for ...
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Timer/PWM (TPM) Module 10.6.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel ...
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TOF — Timer Overflow Flag This flag is set when the TPM counter changes to $0000 after reaching the modulo value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the ...
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Timer/PWM (TPM) Module PS2:PS1:PS0 — Prescale Divisor Select This 3-bit field selects one of eight divisors for the TPM clock input as shown in prescaler is located after any clock source synchronization or clock source selection affects whatever ...
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When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the ...
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Timer/PWM (TPM) Module CHnF — Channel n Flag When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. When channel output compare or edge-aligned ...
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Table 10-3. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it ...
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Timer/PWM (TPM) Module Bit 7 Read: Bit 15 Write: Reset: 0 Figure 10-11. Timer x Channel Value Register High (TPMxCnVH) Bit 7 Read: Bit 7 Write: Reset: 0 Figure 10-12. Timer x Channel Value Register Low (TPMxCnVL) In input capture ...
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Chapter 11 Serial Communications Interface (SCI) Module 11.1 Introduction The MC9S08GB/GT includes two independent serial communications interface (SCI) modules — sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port ...
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Chapter 11 Serial Communications Interface (SCI) Module HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD USER FLASH (GB60 = 61,268 BYTES) (GB32 ...
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Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission ...
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Serial Communications Interface (SCI) Module The MC9S08GB/GT re-synchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate ...
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INTERNAL BUS M 1 × BAUD RATE CLOCK PE PT ENABLE TE SBK TXDIR The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one full character frame of logic high. The ...
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Serial Communications Interface (SCI) Module If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD1 ...
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INTERNAL BUS 16 × BAUD RATE CLOCK DATA RECOVERY FROM RxD1 PIN LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM TRANSMITTER PE PT The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of ...
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Serial Communications Interface (SCI) Module After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full ...
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At the end of a message the beginning of the next message, all receivers automatically force RWU ...
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Serial Communications Interface (SCI) Module When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is ...
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Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into ...
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Serial Communications Interface (SCI) Module Bit 7 Read: 0 Write: Reset: 0 Figure 11-5. SCI Baud Rate Register (SCIxBDH) Bit 7 Read: SBR7 Write: Reset: 0 Figure 11-6. SCI x Baud Rate Register (SCIxBDL) SBR12:SBR0 — Baud Rate Modulo Divisor ...
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SCISWAI — SCI Stops in Wait Mode 1 = SCI clocks freeze while CPU is in wait mode SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes ...
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Serial Communications Interface (SCI) Module 11.10.3 SCI x Control Register 2 (SCIxC2) This register can be read or written at any time. Bit 7 Read: TIE Write: Reset: 0 Figure 11-8. SCI x Control Register 2 (SCIxC2) TIE — Transmit ...
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RE — Receiver Enable When the SCI receiver is off, the RxD1 pin reverts to being a general-purpose port I/O pin Receiver on Receiver off. RWU — Receiver Wakeup Control This bit can be written to ...
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Serial Communications Interface (SCI) Module TC — Transmission Complete Flag TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being transmitted Transmitter idle (transmission activity complete ...
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OR — Receiver Overrun Flag OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the ...
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Serial Communications Interface (SCI) Module RAF — Receiver Active Flag RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. This status flag ...
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NEIE — Noise Error Interrupt Enable This bit enables the noise flag (NF) to generate hardware interrupt requests Hardware interrupt requested when interrupts disabled (use polling). FEIE — Framing Error Interrupt Enable ...
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Serial Communications Interface (SCI) Module 186 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...
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Chapter 12 Serial Peripheral Interface (SPI) Module The MC9S08GB/GT provides one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 2–5. See the appendix for SPI electrical parametric information. When the ...
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Chapter 12 Serial Peripheral Interface (SPI) Module HCS08 CORE BDC CPU HCS08 SYSTEM CONTROL RESET NOTE 4 RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ NOTES 2, 3 RTI COP IRQ LVD USER FLASH (GB60 = 61,268 BYTES) (GB32 ...
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Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select ...
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Serial Peripheral Interface (SPI) Module The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 12-2 shows ...
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SPE ENABLE SPI SYSTEM SHIFT OUT SHIFT LSBFE DIRECTION BUS RATE SPIBR CLOCK CLOCK GENERATOR MASTER/SLAVE MSTR MODE SELECT Freescale Semiconductor Tx BUFFER (WRITE SPI1D) SHIFT SPI SHIFT REGISTER IN Rx BUFFER (READ SPI1D) SHIFT Rx BUFFER Tx BUFFER FULL ...
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Serial Peripheral Interface (SPI) Module 12.2.3 SPI Baud Rate Generation As shown in Figure 12-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor ...
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SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for ...
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Serial Peripheral Interface (SPI) Module When CPHA = 1, the slave begins to drive its MISO output when SS1 goes to active low, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the ...
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When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS1 goes to active low. The first SPSCK edge causes both the master and the ...
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Serial Peripheral Interface (SPI) Module 12.3.3 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag ...
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SPI Control Register 1 (SPI1C1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. Bit 7 Read: SPIE Write: Reset: Figure 12-7. SPI Control Register 1 (SPI1C1) SPIE — SPI Interrupt Enable (for SPRF and ...
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Serial Peripheral Interface (SPI) Module SSOE — Slave Select Output Enable This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS1 pin ...
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BIDIROE — Bidirectional Mode Output Enable When bidirectional mode is enabled by SPI pin control 0 (SPC0 BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the ...
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Serial Peripheral Interface (SPI) Module SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 — SPI Baud Rate Divisor This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in input to this divider comes from the SPI baud rate prescaler ...