MC56F8323MFB60 Freescale Semiconductor, Inc, MC56F8323MFB60 Datasheet
MC56F8323MFB60
Related parts for MC56F8323MFB60
MC56F8323MFB60 Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8322 Rev. 16 04/2007 freescale.com ...
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Version History Rev 1.0 Pre-Release version, Alpha customers only Rev 2.0 Initial Public Release Rev 3.0 Corrected typo in grammar issues Rev 4.0 Added Package Pins to GPIO table in Section 8. Clarification of TRST usage in this device. Replacing ...
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Document Revision History (Continued) Version History Rev 14.0 Replaced “Tri-stated” with an explanation in State During Reset column in Rev. 15 Added the following note to the description of the TMS signal in Note: Rev. 16 Changed the “Frequency Accuracy” ...
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Techncial Data, Rev. 16 Freescale Semiconductor Preliminary ...
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General Description Note: Features in italics are NOT available in the 56F8122 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 32KB Program Flash • 4KB Program ...
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Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 7 1.1. 56F8322/56F8122 Features . . . . . . . . . . . ...
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Part 1 Overview 1.1 56F8322/56F8122 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • ...
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Memory Note: Features in italics are NOT available in the 56F8122 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection • On-chip memory, including a low-cost, high-volume Flash ...
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Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories • On-chip regulators for digital and analog circuitry to lower cost and reduce ...
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PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush ...
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Architecture Block Diagram Note: Features in italics are NOT available in the 56F8122 device and are shaded in the following figures. The 56F8322/56F8122 architecture is shown in 56800E system buses communicate with internal memories and the IPBus Bridge. internal ...
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JTAG / EOnCE pdb_m[15:0] 56800E CHIP TAP Controller TAP Linking Module External JTAG Port cdbr_m[31:0] xdb2_m[15:0] Not available on the 56F8122 device. Note: Flash memories are encapsulated within the Flash Memory Module (FM). Flash control is accomplished by the ...
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CLKGEN (OSC/PLL) (ROSC) Timer A 4 Quadrature Decoder 0 2 FlexCAN 4 2 Not available on the 56F8122 device. Freescale Semiconductor Preliminary To/From IPBus Bridge SCI 1 SPI 0 GPIO A GPIO B GPIO C IPBus Figure 1-2 Peripheral Subsystem ...
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Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
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Product Documentation The documents listed in Table 1-3 and 56F8122 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com/semiconductors/. Topic DSP56800E Detailed description of the 56800E family architecture, ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups, as detailed in Table 2-1 and as illustrated in describes the signal or signals present on a pin. ...
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Power Ground V DDA_ADC Power V SSA_ADC Ground Other CAP Supply Ports EXTAL (GPIOC0) PLL and Clock or XTAL (GPIOC1) GPIO JTAG/ EOnCE Port Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP) Note: V ...
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Power Ground V DDA_ADC Power V SSA_ADC Ground Other CAP Supply Ports EXTAL (GPIOC0) PLL and Clock or XTAL (GPIOC1) GPIO JTAG/ EOnCE Port Figure 2-2 56F8122 Signals Identified by Functional Group (48-Pin LQFP ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). In the 56F8122, after reset, each pin must be configured for the desired function. The initialization software will configure each pin for the function listed ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type EXTAL 32 Input/ (GPIOC0) Schmitt Input/ Output XTAL 33 Output (GPIOC1) Schmitt Input/ Output TCK 39 Schmitt Input TMS 40 Schmitt Input TDI 41 ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type PHASEA0 38 Schmitt Input (TA0) Schmitt Input/ Output (GPIOB7) Schmitt Input/ Output (oscillator_ Output clock) PHASEB0 37 Schmitt Input (TA1) Schmitt Input/ Output (GPIOB6) ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type INDEX0 36 Schmitt Input (TA2) Schmitt Input/ Output (GPIOB5) Schmitt Input/ Output (SYS_CLK) Output HOME0 35 Schmitt Input (TA3) Schmitt Input/ Output (GPIOB4) Schmitt ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type MOSI0 18 Schmitt Input/ Output (GPIOB2) Schmitt Input/ Output MISO0 16 Schmitt Input/ Output (RXD1) Schmitt Input (GPIOB1) Schmitt Input/ Output SS0 15 Schmitt ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type PWMA1 4 Schmitt Output (GPIOA1) Schmitt Input/ Output PWMA2 6 Output (SS1) Schmitt Input (GPIOA2) Schmitt Input/ Output PWMA3 7 Output (MISO1) Schmitt Input/ ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type PWMA4 8 Output (MOSI1) Schmitt Input/ Output (GPIOA4) Schmitt Input/ Output PWMA5 9 Output (SCLK1) Schmitt Input/ Output (GPIOA5) Schmitt Input/ Output FAULTA0 12 ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type V 28 Input/ REFP Output V 27 REFMID V 26 REFN CAN_RX 46 Schmitt Input (GPIOC2) Schmitt Input/ Output CAN_TX 47 Open Drain Output ...
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Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name Pin No. Type TC1 48 Schmitt Input/ Output (RXD0) Output (GPIOC5) Schmitt Input/ Output IRQA 11 Schmitt Input ( RESET 2 Schmitt Input Freescale Semiconductor ...
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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. 3.2 External ...
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Ceramic Resonator (Default also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Refer to the supplier’s ...
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Use of On-Chip Relaxation Oscillator An internal relaxtion oscillator can supply the reference frequency when an external frequency source of crystal is not used. During a boot or reset sequence, the relaxation oscillator is enabled by default, and the ...
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CLK_MODE XTAL Crystal OSC EXTAL PLLCID Prescaler ÷ ( 3.5 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions with the internal Relaxation Oscillator, since the ...
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Part 4 Memory Map 4.1 Introduction The 56F8322 and 56F8122 devices are 16-bit motor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM and Flash memories ...
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Note: Program RAM is NOT available on the 56F8122 device. Table 4-2 Program Memory Map at Reset Begin/End Address P: $1F FFFF P: $03 0000 P: $02 FFFF P: $02 F800 P: $02 F7FF P: $02 1000 P: $02 0FFF ...
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Table 4-3 Interrupt Vector Table Contents Vector Priority Peripheral Number Level core 6 1-3 core 7 1-3 core 9 1-3 core 10 1-3 core 11 1-3 core 14 2 core 15 1 core 16 0 core 17 0-2 LVI 20 ...
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Table 4-3 Interrupt Vector Table Contents Vector Priority Peripheral Number Level TMRC 56 0-2 TMRC 57 0-2 TMRC 58 0-2 TMRC 59 0-2 TMRA 64 0-2 TMRA 65 0-2 TMRA 66 0-2 TMRA 67 0-2 SCI0 68 0-2 SCI0 69 ...
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Data Map Note: Data Flash is NOT available on the 56F8122 device. Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 2000 X:$00 1FFF X:$00 1000 X:$00 0FFF X:$00 0000 1. ...
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Program Memory BOOT_FLASH_START + $0FFF BOOT_FLASH_START = $02_0000 PROG_FLASH_START + $00_3FFF PROG_FLASH_START + $00_3FF7 PROG_FLASH_START + $00_3FF6 32KB PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-5 shows the page and sector sizes used within each Flash memory ...
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EOnCE Memory Map Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — X:$FF FF92 OBAR2 (32 bits) X:$FF FF93 — X:$FF FF94 OBAR1 (24 bits) X:$FF FF95 — X:$FF FF96 OBCR ...
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The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available on the 56F8122 device. Table 4-7 Data Memory Peripheral Base Address Map Summary Peripheral Timer A Timer ...
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Table 4-8 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD ...
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Table 4-9 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR ...
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Table 4-9 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-10 Pulse Width Modulator A Registers Address Map PWM is NOT available in the 56F8122 device Register Acronym ...
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Table 4-11 Quadrature Decoder 0 Registers Address Map Quadrature Decoder is NOT available in the 56F8122 device Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Table 4-12 Interrupt Control Registers Address Map ...
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Table 4-12 Interrupt Control Registers Address Map (Continued) Register Acronym IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL Table 4-13 Analog to Digital Converter Registers Address Map Register Acronym ADCA_CR1 ADCA_CR2 ADCA_ZCC ADCA_LST 1 ADCA_LST ...
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Table 4-13 Analog to Digital Converter Registers Address Map (Continued) Register Acronym ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ...
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Table 4-16 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-17 Serial Peripheral Interface 0 Registers Address Map Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Table 4-18 Serial Peripheral Interface 1 Registers Address Map Register ...
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Table 4-20 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB PLLSR SHUTDOWN OSCTL Table 4-21 GPIOA Registers Address Map Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA Table 4-22 GPIOB Registers Address Map ...
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Table 4-23 GPIOC Registers Address Map Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Table 4-24 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS ...
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Table 4-26 Flash Module Registers Address Map Register Acronym Address Offset FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 Table 4-27 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8122 device Register ...
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Table 4-27 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8122 device Register Acronym FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL ...
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Table 4-27 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8122 device Register Acronym FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH ...
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Table 4-27 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8122 device Register Acronym FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA ...
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Table 4-27 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8122 device Register Acronym FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH ...
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Factory-Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Data Flash (not available on the ...
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Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 ...
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Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...
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Add. Register 15 14 Offset Name IPR0 IPR1 IPR2 FMCBE IPL IPR3 W R SPI0_RCV $4 IPR4 IPL ...
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Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the ...
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Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. ...
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Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ ...
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FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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GPIO_B Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
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SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Interrupt Priority Register 6 (IPR6) Base + $ Read 0 TMRC0 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC_0 IPL)— Bits 15–14 ...
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Interrupt Priority Register 7 (IPR7) Base + $ Read 0 TMRA0 IPL Write RESET Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This ...
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Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. ...
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Fast Interrupt 0 Match Register (FIM0) Base + $ Read Write RESET Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not ...
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Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in ...
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Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address are ...
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IRQ Pending 2 Register (IRQP2) Base + $ Read Write RESET Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the ...
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IRQ Pending 5 Register (IRQP5) Base + $ Read Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The ...
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Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the ...
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Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After ...
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Features The SIM has the following features: • Flash security feature prevents unauthorized access to code/data contained in on-chip flash memory • Power-saving clock gating for peripherals • Three power modes (Run, Wait, Stop) to control power utilization — ...
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Operating Mode Register Bit Type R/W RESET The reset state for the MB bit will depend on the Flash secured state. See detailed information on how the Operating Mode Register (OMR) MA ...
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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 ...
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OnCE Enable (ONCE EBL)—Bit 5 • OnCE clock to 56800E core enabled when core TAP is enabled • OnCE clock to 56800E core is always enabled 6.5.1.3 Software Reset (SW RST)—Bit 4 Writing 1 to ...
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COP Reset (COPR)—Bit 4 When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing this bit position will ...
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Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4. Base + $ Read Write RESET 0 ...
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IRQ—Bit 10 This bit controls the pull-up resistors on the IRQA pin. 6.5.6.4 Reserved—Bits 9–4 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.5 JTAG—Bit 3 This bit ...
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INDEX0 (INDEX)—Bit 7 • Peripheral output function of GPIOB[5] is defined to be INDEX0 • Peripheral output function of GPIOB[5] is defined to be SYS_CLK 6.5.7.5 HOME0 (HOME)—Bit 6 • Peripheral output function ...
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As shown in Figure 6-10, the GPIO has the final control over which pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O. Quad Timer Controlled SCI Controlled Figure 6-10 Overall Control of Pads Using ...
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GPIOB1 (B1)—Bit 5 This bit selects the alternate function for GPIOB1. • MISO0 (default) • RXD1 6.5.8.5 GPIOB0 (B0)—Bit 4 This bit selects the alternate function for GPIOB0. • SS0 (default) • 1 ...
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Reserved—Bits 15–14 This bit field is reserved or not implemented read as 1 and cannot be modified by writing. 6.5.9.2 Analog-to-Digital Converter A Enable (ADCA)—Bit 13 Each bit controls clocks to the indicated peripheral. • ...
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Serial Communications Interface 1 Enable (SCI1)—Bit 5 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.11 Serial Communications ...
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Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral ...
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Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce ...
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Stop and Wait Mode Disable Function Permanent Disable Reprogrammable Disable Clock Select Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop ...
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Part 7 Security Features The 56F8322/56F8122 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized ...
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Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the JTAG/EOnCE. The FM sets this input at ...
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EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0. Using the following equation yields a DIV value of 19 for a ...
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Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User ...
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Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8322 / 56F8122 Pins in italics are NOT available in the 56F8122 device GPIO Function Peripheral Function GPIOA0 PWMA0 GPIOA1 PWMA1 GPIOA2 PWMA2 / SSI GPIOA3 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8322 / 56F8122 Pins in italics are NOT available in the 56F8122 device GPIO Function Peripheral Function GPIOB7 PHASEA0 / TA0 GPIOC0 EXTAL GPIOC1 XTAL ...
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Part 10 Specifications 10.1 General Characteristics The 56F8322/56F8122 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up ...
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Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. Table 10-1 Absolute Maximum Ratings Characteristic Supply voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Internal ...
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Table 10-2 56F8322/56F8122 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural Convection Junction to ambient (@1m/sec) Junction to ambient Natural Convection ...
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Note: The 56F8122 device is guaranteed to 40MHz and specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Supply voltage ...
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DC Electrical Characteristics Note: The 56F8122 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8122 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output ...
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Table 10-6 Power-On Reset Low Voltage Parameters Characteristic 1 POR Trip Point Rising POR Trip Point Falling 2 LVI, 2.5V Supply, trip point 3 LVI, 3.3V supply, trip point Bias Current 1. Both V and V thresholds must be met ...
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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 110mA Wait3 55mA Stop1 700μA Stop2 100μ Output Switching 10.2.1 Voltage Regulator Specifications The 56F8322/56F8122 have two on-chip regulators. ...
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Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200mA load) Line Regulation @ 200mA load (V 33 ranges from 3.0V to 3.6V) DD Short Circuit Current (output shorted to ground) Bias Current Power-down Current Short-Circuit Tolerance (output shorted to ...
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Temperature Sense Note: Temperature Sensor is NOT available in the 56F8122 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain Room Trim Temp. 1,2 Hot Trim Temp. (Industrial) 1,2 Hot Trim Temp. (Automotive) Output Voltage @ ...
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Figure 10-2 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state ...
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External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) Frequency of operation (external clock driver) 3 Clock Pulse Width 4 External clock input rise time 5 External clock input fall ...
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Oscillator Parameters Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode Quiescent ...
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Figure 10-4 Frequency versus Temperature 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All address and data buses described here are internal. Table 10-17 Reset, Stop, ...
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RESET t RAZ PAB PDB Figure 10-5 Asynchronous Reset Timing IRQA Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive) PAB t IDM IRQA General Purpose I/O Pin t IG IRQA Figure 10-7 External Level-Sensitive Interrupt Timing t IW IRQA PAB Figure ...
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Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set up time required for inputs ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-9 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. ...
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Phase A (Input) Phase B (Input) Figure 10-14 Quadrature Decoder Timing 10.12 Serial Communication Interface (SCI) Timing Characteristic 2 Baud Rate 3 RXD Pulse Width 4 TXD Pulse Width 1. Parameters listed are guaranteed by design the ...
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Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8122 device. Characteristic Baud Rate Bus Wake-up detection 1. Parameters listed are guaranteed by design MSCAN_RX CAN receive data pin (Input) 10.14 JTAG Timing Characteristic TCK frequency ...
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TCK (Input – Figure 10-18 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-19 Test Access Port Timing Diagram 10.15 ...
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Table 10-24 ADC Parameters (Continued) Characteristic ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , per pin Input injection current, total V current REFH ADC A current ADC B ...
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Figure 10-20 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...
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Equivalent Circuit for ADC Inputs Figure 10-21 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 closed & S3 open, one input of ...
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C, the internal [dynamic component], is classic C*V 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly ...
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Part 11 Packaging 11.1 56F8322 Package and Pin-Out Information This section contains package and pin-out information for the 56F8322. This device comes in a 48-pin Low-profile Quad Flat Pack (LQFP). Figure 12-1 shows the mechanical parameters for this package, and ...
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Table 11-1 56F8322 48-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 TC0 13 2 RESET 14 3 PWMA0 15 4 PWMA1 DD_IO 6 PWMA2 18 7 PWMA3 19 8 PWMA4 ...
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Package and Pin-Out Information This section contains package and pin-out information for the 56F8122. This device comes in a 48-pin Low-profile Quad Flat Pack (LQFP). Figure 12-1 shows the mechanical parameters for this package, and 48-pin LQFP. TC0 ...
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Table 11-2 56F8122 48-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 TC0 13 2 RESET 14 3 GPIOA0 15 4 GPIOA1 DD_IO 6 SS1 18 7 MISO1 19 8 MOSI1 ...
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AB T 0.200 AC T BASE METAL 0.080 AC T ...
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Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature θJΑ where Ambient temperature for the package ( ...
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small ...
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and V circuits. DD ...
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Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Supply Part Voltage Low-Profile Quad Flat Pack (LQFP) MC56F8322 ...
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Freescale Semiconductor Preliminary 56F8322 Technical Data, Rev. 16 Power Distribution and I/O Ring Implementation 135 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006, 2007. All rights reserved. MC56F8322 Rev. 16 ...