M66592FP Renesas Electronics Corporation., M66592FP Datasheet
M66592FP
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M66592FP Summary of contents
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... M66592FP/WG ASSP (USB2.0 Peripheral Controller) Overview 1 1.1 Overview The M66592 is a USB 2.0 peripheral controller that is compliant with USB (Universal Serial Bus) specification Rev. 2.0 for both Hi-Speed and Full-Speed transfers. This controller has a built-in USB transceiver and supports all of the transfer types defined by the USB specification. The compact package and low power consumption make it ideal for use in mobile devices ...
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1.2.5 Bus interfaces ♦ The user can select either a 1 3.3 V bus interface power supply ♦ 16-bit CPU bus interface • 16-bit separate bus and ...
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... M66592FP (TOP VIEW Package M66592FP : 64pinLQFP (0.5mm pitch) Figure 1.1 Pin layout diagram of M66592FP D6/AD6 29 D5/AD5 28 D4/AD4 27 D3/AD3 26 D2/AD2 25 D1/AD1 A6/ ALE 22 A5 ...
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SD6 SD4 7 SD7 SD5 6 RD_N SOF_N 5 CS_N WR1_N 4 DEND0_N DREQ1_N DREQ0_N DACK0_N 3 DACK1_N VIF /DSTB0_N 2 RST_N AFED33V 1 AFED33G ...
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1.4 Description of pins Table 1.1 describes the controller pins. Category Pin name Name CPU bus D15-0 Data Bus interface AD6-1 Multiplex Address Bus A6-1 Address Bus ALE Address ...
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Category Pin name Name System RST_N Reset signal control TEST Test signal USB bus DP USB D+ data interface DM USB D- data VBUS VBUS VBUS input monitor input ...
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Category SPLIT bus interface DMA bus interface SOF output System control VBUS monitor input *9) When DACKn_N pin is not used, please set DACKA bit of DMAnCFG register as ...
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1.5 Pin function configuration Figure 1.3 shows a diagram of the pin function configuration of the controller. CPU bus interface D15-7,D6-1(/AD6-1),D0 A6/ALE,A5-1 CS_N RD_N WR0_N WR1_N MPBUS Interrupt / ...
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1.6 Block diagram The controller is configured with an analog front end unit (AFE), a protocol engine unit (Prtcl_Eng) that includes an SIE, a pipe control unit (Pipe_Ctrl), a ...
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1.7 An overview of functions 1.7.1 Bus interfaces The controller supports the bus interfaces noted below. 1.7.1.1 External bus interface The controller uses a CPU bus interface to access ...
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1.7.3 USB data transfers The controller is capable of all types of transfers: USB communication control transfers, bulk transfers, and interrupt transfers, as well as isochronous data transfers. The ...
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1.7.6 External elements integration The controller has the following external elements built into it. Also, because the VBUS pin can withstand 5 V, the user system can input the ...
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Registers 2 Bit no. Each register is connected to a 16-bit internal bus. Odd-numbered addresses will use b15 to b8, and even-numbered addresses b7 to b0. Status after reset ...
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2.1 Table of registers Table 2.1 shows the controller registers. Address Symbol SYSCFG 00 SYSSTS 02 DVSTCTR 04 TESTMODE 06 08 PINCFG 0A DMA0CFG 0C DMA1CFG 0E CFIFO 10 ...
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Address Symbol DCPCTR 60 62 PIPESEL 64 PIPECFG 66 PIPEBUF 6E PIPEMAXP 6A PIPEPERI 6C 6E PIPE1CTR 70 PIPE2CTR 72 PIPE3CTR 74 PIPE4CTR 76 PIPE5CTR 78 PIPE6CTR 7A PIPE7CTR ...
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2.2 Table of bit symbols Table 2.2shows the controller bit symbols. Register Odd-numbered addresses Addr name SYSCFG XTAL XCKE 02 SYSSTS 04 DVSTCTR 06 TESTMODE ...
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Register Odd-numbered addresses Addr name PIPESEL 66 PIPECFG TYPE 68 PIPEBUF 6A PIPEMAXP 6C PIPEPERI 6E 70 PIPE1CTR BSTS INBUFM 72 PIPE2CTR BSTS INBUFM 74 ...
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2.3 System control System configuration control register [ SYSCFG ] XTAL XCKE RCKE ...
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System configuration status register [ SYSSTS ] Bit Name ...
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2.4 USB signal control Device state control register [ DVSTCTR ] ...
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2.4.1 USB data bus control Each bit of the DVSTCTR register can be used to control and confirm the state of the USB data bus based on the user ...
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2.5 External input/output control Data pin configuration register [ PINCFG ] LDRV ...
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The DMA0CFG register controls the input/output pins used for the DMA0 interface and the D0FIFO port, and the DMA1CFG register controls the input/output pins used for the DMA1 interface ...
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2.5.1 Output pins drive current control The output pins drive capability should be set using the LDRV bit of the PINCFG register, to match the VIF power supply. The ...
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2.6 FIFO ports The transmission and reception buffer memory of the controller uses the FIFO configuration. The FIFO port registers should be used to access the buffer memory. There ...
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CFIFO port selection register [ CFIFOSEL ] D0FIFO port selection register [ D0FIFOSEL ] D1FIFO port selection register [ D1FIFOSEL ] RCNT REW DCLRM DREQE ...
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CFIFO port control register [ CFIFOCTR ] D0FIFO port control register [ D0FIFOCTR ] D1FIFO port control register [ D1FIFOCTR ] BVAL BCLR FRDY 0 ...
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transaction counter register [ D0FIFOTRN ] D1 transaction counter register [ D1FIFOTRN ] ...
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2.7 Interrupts enabled Interrupts enabled register 0[ INTENB0 ] VBSE RSME SOFE DVSE ...
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«Note» None in particular ...
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Interrupt enabled register 1[ INTENB1 ] Bit Name 15-3 ...
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BRDY interrupt enabled register [ BRDYENB ] Bit Name ...
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2.7.1 Interrupt masks The VBSE , RSME , SOFE , DVSE , CTRE , BEMPE , NRDYE , and BRDYE bits of the INTENB0 register operate as interrupt mask ...
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2.8 SOF control register SOF pin configuration register [ SOFCFG ] ...
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2.9 Interrupt statuses Interrupt status register 0[ INTSTS0 ] VBINT RESM SOFR DVST ...
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BRDY interrupt status register [ BRDYSTS ] Bit Name ...
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2.10 Frame number register Frame number register [ FRMNUM ] OVRN CRCE SOFRM ...
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2.10.1 Isochronous errors With this controller, data transfer errors that occur in isochronous transfers can be confirmed using the OVRN bit and the CRCE bit of the FRMNUM register. ...
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2.11 USB address((low-power recovery) USB address/low-power status recovery register [ RECOVER ] ...
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USB request value register [ USBVAL ] Bit Name ...
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2.13 DCP configuration When data communication is being carried out using control transfers, the default control pipe should be used. DCP configuration register [ DCPCFG ] ...
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DCP control register [ DCPCTR ] BSTS Bit Name ...
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2.14 Pipe configuration register The PIPE1-7 settings should be set using the PIPESEL , PIPECFG , PIPEBUF , PIPEMAXP , PIPEPERI , and PIPExCTR registers. After selecting the pipe ...
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Pipe configuration register [ PIPECFG ] TYPE Bit Name ...
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Pipe buffer setting register [ PIPEBUF ] BUFSIZE ? Bit ...
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Pipe maximum packet size register [ PIPEMAXP ] Bit ...
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PIPE1 control register [ PIPE1CTR ] PIPE2 control register [ PIPE2CTR ] PIPE3 control register [ PIPE3CTR ] PIPE4 control register [ PIPE4CTR ] PIPE5 control register [ PIPE5CTR ...
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Description of Operation 3 3.1 System control and oscillation control This chapter describes the register operations that are necessary to the default settings of the controller, and the registers ...
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... PC is detected, the H/W should be initialized by means of an S/W reset (USBE=0). If “0” is set for the DPRPU bit of the SYSCFG register, the pull-up resistor (or the terminal resistor) of the USB data line is disabled, making it possible to notify the host controller of the device disconnection. M66592FP/WG VBUS RERFIN 3 ...
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3.1.6 Low power consumption control 3.1.6.1 Overview of low-power sleep state In order to reduce power consumption, the controller is equipped with a function for setting a low-power sleep ...
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3.1.6.2 Overvew of Clock stop state This controller is equipped with the setting function of the low power consumption state by clock stop as well as M66291, M66591, and ...
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3.1.6.3 Low-power sleep state The low-power sleep state is set by setting “1” for the PCUT bit of the SYSCFG register. For information on the sequence in which settings ...
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3.1.6.5 Recovering from the clock stop state If any of the events noted below occurs from the clock stop state, the controller notifies the CPU through the INT_N pin. ...
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3.1.7 State transition timing 3.1.7.1 Starting the internal clock supply (from the H/W reset state to the normal operating state) Figure 3.5 shows a diagram of the clock supply ...
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3.1.7.3 Starting the internal clock supply (from the low-power sleep state to the normal operating state) Figure 3.7 shows a diagram of the timing at which the transition from ...
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Figure 3.7 Recovery control timing from the low power sleep state with “ATCKM=1” ...
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3.1.7.4 Stopping the internal clock supply (from the normal operating state to the clock stop state) The timing diagram of the transition The transition should be operated according to ...
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Clock stop (1),(2) recovery XCKE(H/W) RCKE(H/W) PLLC(H/W) SCKE(H/W) INT_N Event Figure 3.9 Recovery control timing from the clock stop state with “ATCKM=1” ...
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3.1.7.6 Starting the internal clock supply (from the clock stop state to the normal operating state : with "ATCKM=0") The timing diagram from the clock stop state to the ...
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3.2 Interrupt functions 3.2.1 An overview of interrupt functions Table 3.7 shows the interrupt functions of the controller. Bit Interrupt name VBINT VBUS interrupt RESM Resume interrupt SOFR Frame ...
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Table 3.8 shows the INT_N pin operations of the controller. If multiple interrupt causes have occurred, the method used for INT_N pin output can be set using the INTL ...
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Figure 3.12 shows a diagram relating to controller interrupts. INT_N Edge / Level Generation Circuit ...
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3.2.2 BRDY interrupt Table 3.9 shows the conditions under which the controller sets “1” pertinent bit of the BRDYSTS register. Under above condition, the controller generats BRDY ...
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With PIPE1-PIPE7, if DMA transfer is being carried out in the reading direction, interrupts can be generated in transfer units, by setting the BFRE bit of the PIPECFG register. ...
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3.2.3 NRDY interrupt If a pipe is under the conditions such as (1), (2)(a), or (2)(b) bellow, the controller sets “1” pertinent bit of the NRDYSTS register. ...
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3.2.4 BEMP interrupt The table below shows the conditions under which BEMP interrupts are generated. The cause of a BEMP for the various pipes should be confirmed using the ...
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3.2.5 Device state transition interrupt Figure 3.16 shows a diagram of the controller device state transitions. The controller controls device states and generates device state transition interrupts. However, recovery ...
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3.2.6 Control transfer stage transition interrupt Figure 3.17 shows a diagram of how the controller handles the control transfer stage transition. The controller controls the control transfer sequence and ...
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3.2.7 Frame refresh interrupt Figure 3.18 shows an example of the SOFR interrupt output timing of the controller. When the frame number is refreshed damaged SOF packet ...
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...
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3.3 Pipe control Table 3.11 shows the pipe setting items of the controller. With USB data transfers, data communication has to be carried out using the logic pipe called ...
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3.3.1 Transfer types The TYPE bit of the PIPEPCFG register is used to specify the type of transfer for the various pipes. The types of transfer that can be ...
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3.3.4 Response PID The PID bit of the DCPCTR register and PIPExCTR register is used to set the response PID for the various pipes. Operation with the various settings ...
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3.4 Buffer memory 3.4.1 Buffer memory allocation Figure 3.19 shows an example of a buffer memory map for the controller. The buffer memory is an area shared by the ...
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3.4.1.1 Buffer status Table 3.12 shows the buffer status. The buffer memory status can be confirmed using the BSTS bit and the INBUFM bit. The access direction for the ...
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3.4.1.3 Buffer areas Table 3.15 shows the FIFO buffer memory map of the controller. The buffer memory has special fixed areas to which pipes are assigned in advance, and ...
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3.4.1.5 Buffer memory specifications (single / double setting) Either a single or double buffer can be selected for PIPE1-5, using the DBLB bit of the PIPExCFG register. The double ...
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3.4.2 FIFO port functions Table 3.16 shows the settings for the FIFO port functions of the controller. When data writing is being accessed, writing data until the buffer is ...
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3.4.2.3 Reading the buffer memory on the SIE side (CFIFO port reading direction) Even in the “FRDY=0” state, when data cannot be read from the buffer memory, confirming the ...
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3.4.3 DMA transfers (DxFIFO port) 3.4.3.1 An overview of DMA transfers For pipes the FIFO port can be accessed using the DMAC. For DMA transfers, there ...
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3.4.3.3 Zero-Length packet addition mode (DxFIFO port writing direction) With this controller possible to add and send one Zero-Length packet after all of the data has been ...
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3.4.3.6 BRDY interrupt timing selection function By setting the BFRE bit of the PIPECFG register possible to keep the BRDY interrupt from being generated when a data ...
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3.4.4 Timing at which the FIFO port can be accessed 3.4.4.1 Timing at which the FIFO port can be accessed when switching pipes Figure 3.23 shows a diagram of ...
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3.5 Data setup timing This section describes the OBUS bit used to select the timing of split bus. With this controller, the timing of the SD0-7 and DEND pin ...
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3.6 Control transfers (DCP) Data transfers of the data stage of control transfers are done using the default control pipe (DCP). The DCP buffer memory is a 256-byte single ...
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3.6.4 Control transfer auto response function The controller automatically responds to a normal SET_ADDRESS request. If any of the following errors occur in the SET_ADDRESS request, a response from ...
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3.7 Bulk transfers (PIPE1-5) The user can select the buffer memory specifications for bulk transfers (single / double buffer setting, or continuous / non-continuous transfer mode setting). The maximum ...
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3.9 Isochronous transfers(PIPE1-2) The controller is equipped with the following functions pertaining to isochronous transfers. (1) Notification of isochronous transfer error information (2) Interval counter (specified by the IITV ...
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3.9.2 DATA-PID Because High-Bandwidth transfers are not supported, the DATA-PID added with the USB 2.0 standard is supported as indicated below. (1) IN direction: (a) DATA0: Sent as data ...
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3.9.4 Setup of data to be transmitted using isochronous transfer With isochronous data transmission using this controller, after data has been written to the buffer memory, a data packet ...
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3.9.5 Isochronous transfer transmission buffer flush If a (u) SOF packet is received without an IN token having been received in the interval frame during isochronous data transmission, the ...
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...
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3.10 SOF interpolation function If data could not be received at intervals (when using Full-Speed operation) or 125 µ s (when using Hi-Speed operation) because an ...
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... Input voltage (VBUS input only (IO) System interface output voltage O Topr Ambient operating temperature tr, tf Input rise, fall times Item M66592FP (LQFP) M66592WG (FBGA) Item Min. 1.35 1.8V supported 1.6 3.3V supported 2.7 3.0 3.0 1.35 1.35 -20 Normal input ...
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4.3 Electrical characteristics(ratings for VIF = 2.7~3.6V, VDD = 1.35~1.65V) Symbol Item V High input voltage IH V Low input voltage IL V High input voltage IH V Low ...
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4.4 Electrical characteristics (ratings for VIF = 1.6~2.0V, VDD = 1.35~1.65V) Symbol Item V High input voltage IH V Low input voltage IL V High input voltage IH V ...
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4.5 Measurement circuit 4.5.1 Pins except for USB buffer block input Elements to P.G. be measured 50Ω 4.5.2 USB buffer block (Full-Speed) VDD DP Elements to be measured DM ...
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4.6 Electrical characteristics (D+/D-) 4.6.1 DC characteristics Symbol Item R Reference resistance REF R FS driver output impedance pull-up resistance pu Input characteristics for Full-Speed operation ...
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4.7 Switching characteristics (VIF = 2.7~3.6V, or 1.6~2.0V) Symbol ta (A) Address access time tv (A) Time that data is valid after address ta (CTRL - D) Time that ...
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4.8 Required timing conditions (VIF = 2.7~3.6V, or 1.6~2.0V) Symbol tsuw (A) Address write setup time tsur (A) Address read setup time tsu (A - ALE) Address setup time ...
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4.9 Timing diagrams Table 4.1 Index for register access timing diagram Bus specification access Separate bus CPU Separate bus CPU Multiplex bus CPU Multiplex bus CPU Access Bus I/F ...
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4.9.1 CPU access timing(when a separate bus is set) 4.9.1.1 CPU access write timing (when a separate bus is set) A6-A1 CS_N Note 1-4 WR1_N, WR0_N Note 1-2 D15-D0 ...
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4.9.2 CPU access timing (when a multiplex bus is set) 4.9.2.1 CPU access write timing (when a multiplex bus is set) 32 tsu (A - ALE) AD6-AD1 / Address ...
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4.9.3 DMA access timing(when a cycle steal transfer and separate bus are set) 4.9.3.1 DMA cycle steal transfer write timing (when a CPU bus address is not used: DFORM=010) ...
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4.9.3.3 DMA cycle steal transfer write timing for strobe use (split bus : DFORM=110, OBUS=1/0) DREQ0_N Note 3-1 DACK0_N STRB0_N Note 3-4 SD7-SD0 DEND0_N 4.9.3.4 DMA cycle steal transfer ...
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4.9.3.5 DMA cycle steal transfer read timing (split bus : DFORM=110,OBUS=0) DMA transfer begins DREQ0_N DACK0_N STRB0_N Note 3-4 td (DREQ - DV) 23 SD7-SD0 td (DREQ - DendV) ...
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4.9.3.6 DMA cycle steal transfer write timing (CPU separate bus setting: DFORM=000) DREQi_N (i=0,1) Note 3-1 50 tsud (A) A6-A1 CS_N Note 3-7 WR0_N, WR1_N Note 3-5 D15-D0 DENDi ...
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4.9.3.8 DMA cycle steal transfer write timing for strobe use (split bus : DFORM=100, OBUS=1/0) DREQi_N (i=0, 1) Note 3-1 DACKi_N (i=0,1) SD7-SD0 DENDi_N (i=0,1) 4.9.3.9 DMA cycle steal ...
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4.9.3.10 DMA cycle steal transfer read timing when strobe is not used(split bus : DFORM=100, OBUS=0) DMA transfer begins DREQi_N (i=0, 1) DACKi_N (i= (DREQ - DV) ...
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4.9.3.11 DMA cycle steal transfer write timing(CPU bus address not used: DFORM=011) DREQi_N (i=0,1) Note 3-1 DACKi_N (i=0,1) Note 3-8 D15-D0 DENDi_N (i=0,1) 4.9.3.12 DMA cycle steal transfer read ...
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Note 3-1: The inactive condition for DREQi_N (i= the control signal. If there is a next DMA transfer, the delay ratings for twh (Dreq) and ten (CTRL-Dreq) ...
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4.9.4 DMA access timing(cycle steal transfer, when a multiplex bus is set) 4.9.4.1 DMA cycle steal transfer write timing (CPU multiplex bus setting: DFORM=000) DREQi_N (i=0,1) tsu (A - ...
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4.9.5 DMA access timing (when burst transfer and separate bus are set) 4.9.5.1 DMA burst transfer write timing (CPU bus address not used: DFORM=010) DREQi_N (i=0,1) DACKi_N (i=0,1) Note ...
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4.9.5.3 DMA burst transfer write timing for strobe use(split bus : DFORM=110, OBUS=1/0) DREQ0_N DACK0_N 48 tw (CTRL_B) DSTRB0_N Note 5-3 43 SD7-SD0 DEND0_N 4.9.5.4 DMA burst transfer read ...
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4.9.5.5 DMA burst transfer read timing for strobe use (split bus : DFORM=110, OBUS=0) DREQ0_N DACK0_N 48 tw (CTRL_B) STRB0_N Note 5 (DREQ - DV) SD7-SD0 Note ...
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4.9.5.6 DMA burst transfer write timing (separate bus setting: DFORM=000) DREQi _N (i=0,1) 50 tsud (A) A6-1 CS_N Note 5 (CTRL_B) WR0_N, WR1_N Note 5-4 43 D15-D0 ...
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4.9.5.8 DMA burst transfer write timing when no strobe is used (split bus: DFORM=100, OBUS=1/0) DREQi_N (i= (CTRL_B) DACKi_N (i= SD7-SD0 DENDi_N (i=0, 1) ...
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4.9.5.10 DMA burst transfer read timing when no strobe is used (split bus: DFORM=100, OBUS=0) DREQi_N (i= (CTRL_B) DACKi_N (i= (DREQ - DV) ...
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4.9.5.11 DMA Burst transfer write timing (CPU bus address not used: DFORM=011) DREQi_N (i=0, (CTRL_B) DACKi_N (i=0,1) 43 D15-D0 DENDi_N (i=0,1) 4.9.5.12 DMA burst transfer read timing ...
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4.9.6 DMA access timing(burst transfer, when a multiplex bus is set) 4.9.6.1 DMA burst transfer write timing (CPU multiplex bus setting: DFORM=000) DREQi_N (i=0, 1) tsu (A - ALE) ...
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Note 6-1: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 6-2: The control signal when reading data is a combination of CS_N ...
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4.10 Interrupt timing INT_N CS_N, WR0_N, WR1_N Note 7-1 Note 7-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active (“L”) overlap period. The ...
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REVISION HISTORY Rev. Date Page 0.80 Jul 12, 2004 1.00 Oct 1, 2004 11 (1.7.5) 16-17 (Table2.2) 20 (2.4) 26 (2.4) 31 (2.7) 47 (2.14) 47 (2.14) 50 (3.1.6.1) 51 (3.1.6.2) 53 (3.1.6.5) 55 (3.1.7.3) 57 (3.1.7.4) 57 (3.1.7.5) 59 ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...