M30805SGP Renesas Electronics Corporation., M30805SGP Datasheet
M30805SGP
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M30805SGP Summary of contents
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REJ09B0187-0100 16 Before using this material, please visit our website to verify that this is the most updated document available. Rev. 1.00 Revision date: Aug. 02, 2005 M16C/80 Group RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES Hardware Manual ...
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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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This hardware manual provides detailes information on the M16C/80 group microcomputers. Users are exoected to have basic knowledge of electric circuits,logical circuits and microcomputers. 2.Register Diagram The symbols,and descriptions,used for bit function in each register are shown below. XXX ...
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M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE NOTES : 1. Before using this material, please visit the our website to ...
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Table of Contents Quick Reference by Address ____________________________________ B-1 1. Overview ___________________________________________________ 1 1.1 Features ......................................................................................................................... 1 1.2 Applications .................................................................................................................. 1 1.3 Pin Configuration .......................................................................................................... 2 1.4 Block Diagram ............................................................................................................... 5 1.5 Performance Outline..................................................................................................... 6 1.6 Pin Description (1) ........................................................................................................ ...
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Interrupt control registers .......................................................................................... 62 9.7 Interrupt Enable Flag (I Flag) ..................................................................................... 64 9.8 Interrupt Request Bit .................................................................................................. 64 9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) ... 64 9.10 Rewrite the interrupt control register ...
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DRAM Controller __________________________________________ 183 26. Programmable I/O Ports ____________________________________ 190 27. Usage Precaution _________________________________________ 208 28. Electrical characteristics ___________________________________ 225 29. Flash Memory Version _____________________________________ 271 30. CPU Rewrite Mode ________________________________________ 274 31. Parallel I/O Mode __________________________________________ 290 32. ...
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Quick Reference by Address Register Address 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 0004 16 Processor mode register 1 0005 16 System clock control register 0 0006 16 System clock control register 1 0007 16 ...
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Quick Reference by Address Address Register 02C0 16 X0 register ,Y0 register 02C1 16 02C2 16 X1 register, Y1 register 02C3 16 02C4 16 X2 register ,Y2 register 02C5 16 02C6 16 X3 register,Y3 register 02C7 16 02C8 16 X4 ...
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Quick Reference by Address Address Register 0340 16 Count start flag 0341 16 Clock prescaler reset flag 0342 One-shot start flag 16 0343 16 Trigger select register 0344 Up-down flag 16 0345 16 0346 16 Timer A0 register 0347 16 ...
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Quick Reference by Address <100-pin version> Address Register 03C0 Port P6 16 03C1 Port P7 16 03C2 Port P6 direction register 16 03C3 Port P7 direction register 16 03C4 Port P8 16 Port P9 03C5 16 03C6 Port P8 direction ...
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Overview The M16C/80 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/80 Series CPU core and are packaged in a ...
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1.3 Pin Configuration Figures 1.1 and 1.2 show the pin configuration (top view) for 100-pin and Figure 1.3 shows the pin configu- ration (top view) for 144-pin. PIN ...
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PIN CONFIGURATION (top view ...
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PIN CONFIGURATION (top view) 108 107 106 105 104 103 102 P1 /D 109 110 P0 /D 111 ...
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1.4 Block Diagram Figure 1 block diagram of the M16C/80 group. I/O ports Port P0 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 ...
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1.5 Performance Outline Table 1 performance outline of M16C/80 group. Table 1.1 Performance outline of M16C/80 group Item Number of basic instructions Shortest instruction execution time ...
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... Overview M30805SGP-BL M30803SFP/GP-BL M30802SGP-BL M30800SFP/GP-BL M30805SGP M30803SFP/GP M30802SGP M30800SFP/GP External ROM version Remarks Mask ROM version Flash memory version External ROM version External ROM version with built-in boot loader ...
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Type No – – BL Figure 1.6 Product Numbering System Page ...
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1.6 Pin Description (1) Pin name Signal name Power supply input CNV CNV SS SS Reset input RESET X Clock input IN X ...
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Pin Description (2) Pin name Signal name I/O port ...
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Pin Description (3) Pin name Signal name P11 to P11 I/O port P11 0 4 (Note) P12 to P12 I/O port P12 0 7 (Note) P13 to P13 ...
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Memory Figure 2 memory map of the M16C/80 group. The address space extends the 16 Mbytes from ad- dress 000000 to FFFFFF 16 there is ...
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Central Processing Unit (CPU) The CPU has a total of 28 registers shown in Figure 3.1. Eight of these registers (R0, R1, R2, R3, A0, A1, SB ...
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(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are ...
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(9) Save PC register (SVP) This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is generated. (10) Vector register ...
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(17) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3.2 shows the flag register (FLG). The following ...
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• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification eight processor interrupt ...
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Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software ...
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Table 4.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 4.3 and 4.4 show the internal status of the microcomputer immediately ...
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(1) Processor mode register 0 (Note1) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Wait control register Address ...
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(68) Interrupt cause select register (69) UART3 special mode register 3 (70) UART3 special mode register 2 UART3 special mode register (71) UART3 transmit/receive mode register (72) UART3 ...
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SFR 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 (PM0) 0004 16 Processor mode register 1(PM1) 0005 16 System clock control register 0 ...
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02C0 16 X0 register (X0R) Y0 register (Y0R) 02C1 16 02C2 16 X1 register (X1R) Y1 register (Y1R) 02C3 16 02C4 16 X2 register (X2R) Y2 register (Y2R) ...
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0340 16 Count start flag (TABSR) 0341 Clock prescaler reset flag (CPSRF) 16 0342 16 One-shot start flag (ONSF) 0343 Trigger select register (TRGSR) 16 0344 Up-down flag ...
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<100-pin version> 03C0 16 Port P6 (P6) 03C1 Port P7 (P7) 16 03C2 Port P6 direction register (PD6) 16 03C3 Port P7 direction register (PD7) 16 03C4 Port ...
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Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 0004 microcomputer. A software reset has the same effect as a hardware reset. The ...
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Processor mode register 0 (Note Bit symbol Reserved bit Note 1: Set bit 1 of the protect register ...
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Processor mode register 1 (Note 1) :Mask ROM version Note 1: Set bit 1 of the protect register (address ...
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Figure 6.3 Memory maps in each processor mode Page ...
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Bus 7.1 Bus Settings The BYTE pin, bit the external data bus width control register (address 000B processor mode register 0 (address 0004 ...
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The default after a reset is the separate bus configuration, and the full CS space multiplex bus configu- ration cannot be selected in microprocessor mode. If you select ...
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Table 7.3 Each processor mode and port function Processor Single-chip mode mode Multiplexed bus space CS1 or CS2 : multiplexed select bit bus, and the other : separate ...
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7.2 Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the ...
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The chip select signal turns “L” (active) in synchronize with the address bus. However, its turning “H” depends on the area accessed in the next cycle. Figure 7.2 ...
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(3) Read/write signals With a 16-bit data bus, bit 2 of the processor mode register 0 (address 0004 _____ ________ ______ RD, BHE, and WR signals or RD, ...
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(4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. The ALE output pin is ...
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Separate bus (2 wait) 1st cycle BCLK RD (Note (i RDY Multiplexed bus (2 wait) 1st cycle BCLK RD (Note (i=0 to ...
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(6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places ...
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(9) DRAM controller signals (RAS, CASL, CASH, and DW) Bits 1, 2, and 3 of the DRAM control register (address 0004 DRAM controller. The DRAM controller signals are ...
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Wait control register Note 1: When using the multiplex bus configuration, there are two waits regardless of whether you have ...
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< Separate bus (no wait) > BCLK Write signal Read signal Data bus Address bus (Note 2) Chip select (Note 2,3) < Separate bus (with wait) > BCLK ...
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< Separate bus (with 3 wait) > BCLK Write signal Read signal Data bus Address (Note 2) Chip select (Note 2,3) < Multiplexed bus (with 2 wait) > ...
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Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 8.1 Main ...
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8.2 Clock Control Figure 8.3 shows the block diagram of the clock generating circuit. CM10 “1” Write signal RESET Software reset NMI Interrupt request level judgment output WAIT ...
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The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a ...
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...
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Main clock division register (Note Bit symbol Nothing is assigned. When write, set "0". When read, their contents are ...
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Table 8.2 Clock output setting (single chip mode) BCLK output function Clock output function select select bit PM07 CM01 0 Note ...
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Table 8.4 Port status during stop mode Pin _______ Address bus, data bus, CS0 to CS3, BHE _____ ______ ________ _________ ______ RD, WR, WRL, WRH, DW, CASL, ...
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8.5 Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and ...
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8.6 Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 8.6 shows the operating modes corresponding ...
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Note: When count source of BCLK is changed from clock A to clock B (X needs to be stable before changing. Please wait to change modes until after ...
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8.7 Power Saving In Power Save modes, the CPU and oscillator stop and the operating clock is slowed to minimize power dissipation by the CPU. The following outlines ...
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Transition of stop mode, wait mode All oscillators stopped CM10=“1” Stop mode Interrupt Interrupt CM10=“1” All oscillators stopped CM10=“1” Stop mode Interrupt Note 3 Note 1: Switch clocks ...
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8.8 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure ...
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Interrupt Outline 9.1 Types of Interrupts Figure 9.1 lists the types of interrupts. Software Interrupt Hardware *1 Peripheral I/O interrupts are generated by the peripheral functions built ...
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9.2 Software Interrupts Software interrupts are generated by some instruction that generates an interrupt request when ex- ecuted. Software interrupts are nonmaskable interrupts. (1) Undefined-instruction interrupt This interrupt ...
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9.3 Hardware Interrupts There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts. (1) Special interrupts Special interrupts are nonmaskable interrupts. • Reset A reset ...
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9.4 High-speed interrupts High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3 cycles. When a high-speed interrupt is received, ...
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• Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFFDC of ...
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Table 9.3 Interrupt causes (variable interrupt vector addresses) Vector table address Software interrupt number Address (L) to address (H) Software interrupt number (Note 1) ...
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9.6 Interrupt control registers Peripheral I/O interrupts have their own interrupt control registers. Figure 9.3 shows the interrupt control registers. When using an interrupt to exit Stop mode ...
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Interrupt control register Bit symbol Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: This ...
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Exit priority register Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note 1: Exits the ...
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Table 9.4 shows how interrupt priority levels are set. Table 9.5 shows interrupt enable levels in relation to the processor interrupt priority level (IPL). The following lists the ...
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9.11 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed ...
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Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that consists of 24* cycles. Time (b) is shown in Table 9.6. * ...
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9.13 Changes of IPL When Interrupt Request Acknowledged When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set to the processor interrupt ...
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9.15 Return from Interrupt Routine As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter ...
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High Priority level of each interrupt DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission UART0 reception UART1 transmission UART1 reception ...
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______ 9.18 INT Interrupts ________ ________ INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control register select the input signal ...
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______ 9.19 NMI Interrupt ______ An NMI interrupt is generated when the input to the non-maskable external interrupt. The pin level can be checked in ...
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9.21 Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Four address match interrupts can ...
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9.22 Precautions for Interrupts (1) Reading addresses 000000 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the ...
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Figure 9.12 Switching condition of INT interrupt request (5) Rewrite the interrupt control register • When a instruction to rewrite the interrupt control register is executed but the ...
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Example 1) Interrupt_A: pushm R0,R1,R2,R3,A0,A1 ; <---- •••• Example 2) mov.b #0,TA0IC nop nop nop nop nop nop nop Example 3) fset I nop nop nop Example 4) ...
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Example 5) If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple interrupts with interrupt C, the above processing is required ...
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10. Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve ...
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Watchdog timer control register Watchdog timer start register ...
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11. DMAC This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC is a function ...
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Table 11.1 DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred 128 Kbytes (with 16-bit transfers Kbytes (with 8-bit transfers) DMA ...
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DMAi request cause select register ( 3)(Note Nothing is assigned. When write, set "0". When read, ...
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DMA mode register 0 (CPU internal register DMA mode register 1 (CPU internal register ...
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DMAi transfer count register ( (CPU internal register) b15 DMAi transfer count reload register ( (CPU internal register) b15 Figure ...
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DMAi memory address register ( (CPU internal register) b23 Note 1: When setting DMA2 and DMA3, set "1" to the register bank select flag ...
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(1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus ...
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(1) •When 8-bit data is transferred •When 16-bit data is transferred on a 16-bit data bus and the source address is even BCLK Address CPU use bus RD ...
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(2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the number of DMAC transfer cycles. The number ...
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(1) Internal factors The DMAi request flag is set to “1” in response to internal factors at the same time as the interrupt request bit of the interrupt ...
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Precautions for DMAC (1) Do not clear the DMA request bit of the DMAi request cause select register. In M16C/80, when a DMA request is generated while the ...
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Set the following SFR registers: •DMAiSFR address register •DMAI memory address reload register •DMAi memory address register •DMAi transfer count reload register •DMAi transfer count register 5. ...
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12. Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Count ...
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1 C32 TB0 IN TB1 IN TB2 IN TB3 IN TB4 IN TB5 IN Figure 12.2 Timer B block ...
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13. Timer A Figure 13.1 shows the block diagram of timer A. Figures 13.2 to 13.4 show the timer A-related registers. Except in event counter mode, timers A0 ...
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Timer Ai register (Note 1) (b15) (b8) b7 b0b7 Count start flag Up/down flag (Note ...
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One-shot start flag Trigger select register Clock prescaler reset flag ...
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(1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 13.1) Figure 13.5 shows the timer Ai mode register in timer mode. ...
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(2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single- phase external ...
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Table 13.3 Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source • Two-phase pulse signals input to ...
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Timer Ai mode register (When using two-phase pulse signal processing Note 1: Set the corresponding ...
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• Counter Resetting by Two-Phase Pulse Signal Processing This function resets the timer counter to “0” when the Z-phase (counter reset) is input during two- phase pulse signal ...
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TA3 OUT (A phase) TA3 IN (B phase) Count source INT2 (Note) (Z phase) Count value Note: When the rising edge of INT2 is selected Figure 13.9 The ...
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(3) One-shot timer mode In this mode, the timer operates only once. (See Table 13.4) When a trigger occurs, the timer starts up and continues operating for a ...
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(4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 13.5) In this mode, the counter functions ...
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Condition : Reload register = 0003 (rising edge of TA Count source “H” TA pin iIN input signal “L” “H” PWM pulse output from TA pin iOUT “L” ...
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14. Timer B Figure 14.1 shows the block diagram of timer B. Figures 14.2 and 14.3 show the timer B-related registers. Use the timer Bi mode register (i ...
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Timer Bi register (Note) (b15) (b8 Count start flag Timer B3 count start flag b7 ...
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(1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 14.1) Figure 14.4 shows the timer Bi mode register in timer mode. ...
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(2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 14.2) Figure 14.5 shows the timer Bi mode ...
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(3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 14.3) Figure 14.6 shows ...
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When measuring measurement pulse time interval from falling edge to falling edge Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches ...
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15. Three-phase motor control timers’ functions Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. Figures 15.1 ...
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Three-phase output buffer register Nothing is assigned. When write, set "0". When read, its content is "0". Note: When ...
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Timer Ai register (Note1) (b15) (b8 Timer Ai-1 register (Note (b15) (b8 Trigger select register ...
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Three-phase motor driving waveform output mode (three-phase PWM output mode) Setting “1” in the mode select bit (bit 2 at 0308 mode that uses four timers A1, A2, ...
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Figure 15.5 shows the block diagram for three-phase waveform mode. In “L” active output polarity in three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W ...
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Figure 15.5 Block diagram for three-phase waveform mode Page 117 ...
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Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit 6 at 0308 ). Also, set “1” ...
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phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform ...
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Assigning certain values to DU0 (bit 0 at 030A and DUB1 (bit 1 at 030B 16 ___ the U phase alone, to fix U phase to “H”, to ...
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Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit 6 at 0308 ). Also, set “0” in ...
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carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m U phase ...
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Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to “H” as shown ...
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16. Serial I/O Serial I/O is configured as five channels: UART0 to UART4. UART0 to 4 UART0 to UART4 each have an exclusive timer to generate a transfer ...
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(UART0) RxD0 Clock source selection f 1 Internal External Clock synchronous type (when internal clock is selected) CLK polarity CLK0 reversing circuit CTS/RTS selected ...
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(UART3) RxD polarity RxD3 reversing circuit Clock source selection f 1 Internal External Clock synchronous type (when internal clock is selected) CLK polarity CLK3 ...
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PAR 1SP disabled SP SP PAR 2SP PAR RxDi enabled PAR 2SP enabled SP SP PAR 1SP PAR disabled “0” Figure 16.3 Block diagram of ...
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reverse RxD data RxDi reverse circuit Reverse 1SP SP SP PAR 2SP PAR enabled 2SP SP SP PAR 1SP PAR disabled “0” Figure 16.4 ...
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UARTi transmit buffer register (Note) (b15) (b8 UARTi receive buffer register (b8) (b15 UARTi bit rate generator (Note ...
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UARTi transmit/receive mode register UiMR(i=0,1) Bit symbol SMD0 Serial I/O mode select bit SMD1 SMD2 CKDIR STPS PRY PRYE SLEP ...
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UARTi transmit/receive control register UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS TXEPT CRD NCH CKPOL UFORM Transfer format select bit ...
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UARTi transmit/receive control register Bit symbol CLK0 CLK1 CRS TXEPT CRD NCH CKPOL UFORM Transfer format select bit Note ...
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UARTi transmit/receive control register Bit symbol Nothing is assigned. When write, set "0". When read, ...
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UART transmit/receive control register Bit symbol U0IRS U1IRS U0RRM U1RRM Nothing is assigned. When write, set "0". When read, ...
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UARTi special mode register symbol IICM2 CSC SWC STC SWC2 SCL wait output bit 2 SDHI SHTC Start/stop condition ...
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UART2 special mode register Note 1: These bits are used for SDA Otherwise, must set to "000". Note 2: ...
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17. Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 17.1 and 17.2 list the specifications ...
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Table 17.2 Specifications of clock synchronous serial I/O mode (2) Item Error detection • Overrun error (Note 1) Select function • CLK polarity selection • LSB first/MSB first ...
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UARTi transmit/receive mode registers Note 1: Select CLK output by the corresponding function select registers A, ...
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Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple ...
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• Example of transmit timing (when internal clock is selected) Transfer clock “1” Transmit enable “0” Data is set in UARTi transmit buffer register bit (TE) “1” Transmit ...
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(a) Polarity select function As shown in Figure 17.3, the CLK polarity select bit (bit 6 at addresses 0364 032C , 02FC ) allows selection of the polarity ...
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(c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a ...
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18. Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 18.1 and ...
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Table 18.2 Specifications of UART Mode (2) Item Error detection • Overrun error (Note) • Framing error • Parity error • Error sum flag Select function • Separate ...
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UARTi transmit / receive mode registers Bit symbol Note: Set the corresponding port function select register A to I/O port. ...
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Table 18.3 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note ...
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• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock “1” Transmit enable bit(TE) “0” “1” Transmit buffer empty ...
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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source “1” Receive enable bit “0” RxDi Transfer clock ...
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(c) Function for switching serial data logic (UART2 to UART4) When the data logic select bit (bit 6 of address 033D in writing to the transmission buffer register ...
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Clock-asynchronous serial I/O mode (compliant with the SIM interface 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the ...
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Clock-asynchronous serial I/O mode (compliant with the SIM interface Transfer Clock "1" Transmit rnable bit (TE) "0" Transmit enable "1" empty flag (TI) "0" Start TxDi ST ...
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Clock-asynchronous serial I/O mode (compliant with the SIM interface (a) Function for outputting a parity error signal During reception, with the error signal output enable bit (bit ...
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Clock-asynchronous serial I/O mode (compliant with the SIM interface Figure 19.4 shows the example of connecting the SIM interface. Connect TxDi and RxDi and apply pull- up. ...
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20. UARTi Special Mode Register ( UART2 to UART4 operate the IIC bus interface (simple IIC bus) using the UARTi special mode register (addresses ...
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UARTi special mode register Bit symbol IICM ABC BBS LSYN ABSCS ACSE SSS Nothing is assigned. When write, set "0". ...
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/TXD /SDA 0 2 Selector Noize Filter P7 /RXD /SCL 1 2 Noize Filter Noize Filter P7 /CLK 2 2 Figure 20.2 Functional block diagram for I ...
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The start condition detection interrupt is generated when the fall at the SDA2 pin (P7 while the SCL2 pin (P7 rise at the SDA2 pin (P7 The acknowledge ...
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Bus collision detect sampling clock select bit (Bit 4 of the UARTi special mode register) 0: Rising edges of the transfer clock CLKi TxDi/RxDi Timer Ai 2. ...
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UARTi Special Mode Register 2(i (Address 0336 Bit 0 is the IIC mode select bit 2. Table 20.2 gives control changes by bit when the IIC ...
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Table 20.2 Functions changed by I Function Interrupt no. 33, 35, 37 factor Interrupt no. 34, 36, 38 factor DMA factor Data transfer timing from UARTi (i = ...
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(2) Serial Interface Special Function UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure 20.5). The master outputting the transfer ...
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UARTi special mode register 3 (i=3, Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi ...
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Clock Phase Setting With bit 1 of UARTi special mode register 3 (addresses 0325 UARTi transmission-reception control register 0 (addresses 032C combinations of transfer clock phase and polarity ...
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"H" SS input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" High- inpedance Data input timing Figure 20.8 ...
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21. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. Pins P10 direction registers of these pins for ...
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1/2 V REF VCUT=0 Resistance ladder AV SS VCUT=1 Successive conversion register Addresses (0381 , 0380 ) A/D register 0(16 (0383 , 0382 ) ...
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A/D control register 0 (Note Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Note 1: ...
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A/D control register 2 (Note Bit symbol Reserved bit Nothing is assigned. When write, set "0". When ...
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(1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conver- sion. Table 21.2 shows the specifications ...
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(2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A/D conversion. Table 21.3 shows the specifications of ...
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(3) Single sweep mode In single sweep mode, the pins selected using the A/D sweep pin select bit are used for one-by-one A/D conversion. Table 21.4 shows the ...
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(4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A/D sweep pin select bit are used for repeat sweep A/D conversion. Table ...
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(5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A/D conversion with emphasis on the pin or pins selected using the A/D ...
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(a) Sample and hold Sample and hold is selected by setting bit 0 of the A/D control register 2 (address 0394 sample and hold is selected, the rate ...
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22. D/A Converter This is an 8-bit, R-2R type D/A converter. The microcomputer contains two independent D/A converters of this type. D/A conversion is performed when a value ...
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D/A control register D/A register Figure 22.2 D/A control register D/A0 output enable bit "0" DA0 "1" ...
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23. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom- puter uses a generator polynomial of CRC_CCITT (X The ...
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b15 (1) Setting 0000 16 (2) Setting 01 16 b15 The code resulting from sending 1), becomes the ...
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24. XY Converter XY conversion rotates the matrix data by 90 degrees. It can also be used to invert the top and bottom of the ...
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The reading of the Yi register is controlled by the read-mode set bit (bit 0 at address 02E0 When the read-mode set bit (bit 0 at address 02E0 ...
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When the read-mode set bit (bit 0 at address 02E0 by reading the Yi register. Figure 24.4 shows the conversion table when the read mode set bit = ...
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25. DRAM Controller There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of DRAM. Table 25.1 shows ...
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• DRAM Controller Multiplex Address Output The DRAM controller outputs the row addresses and column addresses as a multiplexed signal to the address bus ...
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• Refresh _______ The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set register (address 0041 ). The refresh signal ...
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The DRAM self-refresh operates in STOP mode, etc. When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction, simultaneously set the ...
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< Read cycle (wait control bit = 0) > BCLK Row MA0 to MA12 address RAS CASH CASL ' (EDO mode) Note ...
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< Read cycle (wait control bit = 1) > BCLK MA0 to MA12 RAS CASH CASL ' (EDO mode) Note : Only ...
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BCLK RAS CASH CASL DW Note : Only CASL is operating in 8-bit data bus width. BCLK RAS CASH CASL DW Note : Only CASL is operating in ...