IN74AC374DW Integral Corp., IN74AC374DW Datasheet

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IN74AC374DW

Manufacturer Part Number
IN74AC374DW
Description
Manufacturer
Integral Corp.
Datasheet
Octal 3-State
Noninverting D Flip-Flop
High-Speed Silicon-Gate CMOS
HC/HCT374. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
with the rising edge of the Clock. The Output Enable input does not
affect the states of the flip-flops, but when Output Enable is high, the
outputs are forced to the high-impedance state; thus, data may be
stored even when the outputs are not enabled.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA; 0.1 μA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
The IN74AC374 is identical in pinout to the LS/ALS374,
Data meeting the setup and hold time is clocked to the outputs
LOGIC DIAGRAM
PIN 10 = GND
PIN 20=V
CC
X = don’t care
Z = high impedance
Output
Enable
H
L
L
L
ORDERING INFORMATION
T
FUNCTION TABLE
L,H,
PIN ASSIGNMENT
TECHNICAL DATA
A
IN74AC374DW SOIC
Inputs
IN74AC374N Plastic
Clock
= -40° to 85° C for all
X
IN74AC374
packages
D
H
X
X
L
change
Output
no
Q
H
L
Z
1

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IN74AC374DW Summary of contents

Page 1

... LOGIC DIAGRAM PIN 20=V PIN 10 = GND Output Enable don’t care Z = high impedance TECHNICAL DATA IN74AC374 ORDERING INFORMATION IN74AC374N Plastic IN74AC374DW SOIC T = -40° to 85° C for all A packages PIN ASSIGNMENT FUNCTION TABLE Inputs Output Clock L,H, ...

Page 2

MAXIMUM RATINGS Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin Output Sink/Source Current, ...

Page 3

DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High- IH Level Input Voltage V Maximum Low - IL Level Input Voltage V Minimum High- OH Level Output Voltage V Maximum Low- OL Level Output Voltage I Maximum Input IN Leakage Current ...

Page 4

AC ELECTRICAL CHARACTERISTICS Symbol Parameter f Maximum Clock Frequency (Figure 1) max t Propagation Delay, Clock to Q (Figure 1) PLH t Propagation Delay, Clock to Q (Figure 1) PHL t Propagation Delay, Output Enable to Q PZH (Figure 2) ...

Page 5

Figure 1. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM IN74AC374 Figure 2. Switching Waveforms 5 ...

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