CS4327-KS Cirrus Logic, Inc., CS4327-KS Datasheet
CS4327-KS
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CS4327-KS Summary of contents
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... The CS4327 also includes an extremely flexible serial port utilizing mode select pins to support multiple inter- face formats. The master clock can be either 256, 384, or 512 times the input sample rate, supporting various audio environments. ORDERING INFO CS4327-KS CDB4327 DEM0 DEM1 VA ...
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... THD -87 - - (Note kHz - - 0 - 0.5465 72 (Note CS4327 = VD Typ Max Unit - 70 ° 100 - 100 - - - - - - -37 - ...
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... Power Supply Rejection Ratio (1 kHz) Allowable Junction Temperature Junction to Ambient Thermal Impedance DS190F1 (Continued) Symbol 0. ° C; Internal SCLK; Full-Scale Output A Symbol Normal Operation IA+ ID+ (IA+) + (ID+) Power Down (IA+) + (ID+) Normal Operation Power-down PSRR JA CS4327 Min Typ Max Unit - 0 ±2 ± 200 - ppm/°C 1.0 1.05 Vrms 6 ...
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... Symbol Fs MCLK/LRCK = 512 MCLK/LRCK = 512 MCLK/LRCK = 384 MCLK/LRCK = 384 MCLK/LRCK = 256 MCLK/LRCK = 256 t sclkl t sclkh t sclkw t slrd t slrs t sdlrs t sdh SCLK/LRCK = 64 t sclkw t sclkr t sdlrs t sdh MCLK/LRCK = 384 t sdh CS4327 Min Typ Max Unit kHz ...
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... LRCK SCLK SDATA LRCK SDATA *INTERNAL SCLK * The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4327 DS190F1 t slrs sclkl slrd t sdh t sdlrs External Serial Mode Input Timing t sclkr t sclkw t t sdlrs sdh Internal Serial Mode Input Timing. ...
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... C; VD ±5%) A Symbol (AGND = DGND = 0 V; all voltages with respect to ground.) Symbol Positive Analog VA+ Positive Digital VD+ |VA IND stg Symbol Positive Analog VA+ Positive Digital VD+ |VA+ - VD+| CS4327 Min Typ Max Unit 2 0 ±10.0 µ Min Max Unit -0.3 6.0 V -0.3 6 ...
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... DIF0 11 DIF1 AOUTL CS4327 7 LRCK 9 SCLK* CMFILT 10 SDATA 1 DEM0 2 DEM1 12 AUTO_MUTE AOUTR 8 MCLK DGND AGND SCLK must be connected to DGND for operation in Internal SCLK Mode Figure 1. Typical Connection Diagram +5 V Analog + 1 µF 0.1 µF 3 VA+ 14 ANALOG FILTER µF 13 ANALOG FILTER CS4327 7 ...
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... GENERAL DESCRIPTION The CS4327 is a complete stereo digital-to-analog system including digital interpolation, 128x fourth- order delta-sigma digital-to-analog conversion, and analog filtering, see Figure 2. This architecture pro- vides a high insensitivity to clock jitter. The DAC converts digital data at any input sample rate be- tween 1 and 50 kHz, including the standard audio rates of 48, 44 ...
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... LRCK frequency ratio has been detected, the phase and frequency relationship between the two clocks must remain fixed. If during any LRCK this rela- tionship is changed, the CS4327 will reset. Table 1 illustrates the standard audio sample rates and the required MCLK frequencies. ...
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... Figure 4. Digital Input Format Figure 5. Digital Input Format 3. CS4327 Right Channel Right Channel ...
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... Auto Mute An auto-mute function is useful for applications, such as compact disk players, where the idle chan- nel noise must be minimized. The CS4327 will au- tomatically initiate a mute for an idle channel input, where idle channel is defined as an input of static 1’s or static 0’s during 8192 consecutive LRCK cy- cles ...
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... Figure 9. CS4327 Combined Digital and Analog Filter Transition Band 12 dependent and will scale with Fs. Note that the re- sponse plots have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs, such as 48 kHz. Figure 8. CS4327 Combined digital and Analog Filter Passband Response CS4327 DS190F1 ...
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... Vpp (1 Vrms) output with a 2.3 volt common mode for a full scale digital in- put. The CS4327 filter is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the Figure 11 ...
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... All mode pins which re- quire VD+ should be connected to pin 6 of the CS4327. All mode pins which require DGND should be connected to pin 5 of the CS4327. Pins 4 and 5, AGND and DGND, should be connected to- gether at the CS4327. DGND for the CS4327 should not be confused with the ground for the dig- ital section of the system ...
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... Figure 13. Frequency Response Figure 15. 0 dBFS FFT Figure 17. -60 dBFS FFT DS190F1 CS4327 Figure 14. THD+N vs. Amplitude Figure 16. -20 dBFS FFT Figure 18. Fade-to-Noise Linearity 15 ...
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... AOUTL - Left Channel Analog Output, PIN 14. Analog output connection for the Left channel outputs. Nominally 1 Vrms for full-scale digital input signal DEM0 CMFILT DEM1 2 15 DIF0 VA AOUTL AGND 4 13 AOUTR 5 12 DGND AUTO_MUTE 6 11 VD+ DIF1 7 10 LRCK SDATA 8 9 MCLK SCLK CS4327 DS190F1 ...
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... Two’s complement MSB-first serial data of either 16 bits is input on this pin. The data is clocked into the CS4327 via the SCLK clock, and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0 and DIF1 ...
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... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 18 CS4327 DS190F1 ...
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... L 0.63 0.90 1.03 N see other table 0° 4 ° MILLIMETERS N MIN NOM MAX 16 5.90 6.20 6.50 20 6.90 7.20 7.50 28 9.90 10.20 10.50 CS4327 INCHES MIN NOM MAX Note 2. 0.084 0.002 0.006 0.010 0.064 0.070 0.074 0.009 0.012 0.015 2, 3 see other table 1 0.291 0.307 0.323 0.197 0.209 0.220 1 0.024 0.026 0.027 0.025 0.035 0.040 see other table 8° ...
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Notes • ...
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... Analog outputs are provided via RCA connectors for both channels. The CS8412 digital audio receiver I.C. provides the system timing necessary to operate the CS4327 and will accept AES/EBU, S/PDIF, and EIAJ-340 compat- ible audio data. The evaluation board may also be configured to accept external timing signals for opera- tion in a user application during system development ...
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... Figure 1. Notice that the the system diagram also includes the inter- connections between the partitioned schematics. CS4327 Digital to Analog Converter A description of the CS4327 is included in the CS4327 data sheet. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 8 ...
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... VD1+ should not used for any additional digital circuitry. Ideally, all mode pins which require VD1+ should be connected to pin 6 of the CS4327 and all mode pins which require DGND should con- nected to pin 5 of the CS4327. AGND and DGND, Pins 4 and 5, are connected together at the CS4327 ...
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... SCLK CS4327 SCLK Mode Selects source of de- DEM_8412 emphasis control * Default setting from factory 24 +5 Volts for the CS4327, CS8412, and digital input input +/- 12 Volts for analog filter section input ground connection from power supply input digital audio interface input via coax ...
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... Digital Audio Interface fig 8 De-emphasis Mode Selection fig 3 DS190DB1 I/O for Clocks and Data fig 6 MCLK LRCK SCLK SDATA CS4327 fig 2 Auto Mute Select and Format Select fig 5 Figure 1. System Block Diagram and Signal Flow CDB4327 AOUTL Analog Filter AOUTR fig 5 25 ...
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... Figure 2. CS4327 and Connections ...
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DB190DB1 Figure 3. De-Emphasis Mode Selection Figure 4. Auto-Mute Select and Format Select CDB4327 27 ...
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NOTE: Right Channel components in parentheses Figure 5. 2-Pole Analog Filter Figure 6. I/O Interface for Clocks and Data CDB4327 DB190DB1 ...
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OPT1 Toshiba TORX173 optical receiver available from Insight Electronics DB190DB1 Figure 7. Digital Audio Input CDB4327 29 ...
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Note: U2 and U4 can not be installed simultaneously Figure 8. CS8412 and Connections ...
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DB190DB1 Figure 9. Power Supply Connections CDB4327 31 ...
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Figure 10. CDB4327 Component Side Silkscreen CDB4327 DB190DB1 ...
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DB190DB1 Figure 11. CDB4327 Component Side (top) CDB4327 33 ...
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Figure 12. CDB4327 Solder Side (bottom) CDB4327 DB190DB1 ...
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Notes • ...
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