AT86RF211S ATMEL Corporation, AT86RF211S Datasheet
AT86RF211S
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AT86RF211S Summary of contents
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Features • High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4 ™ ZigBee and ISM Applications • Industry Leading Link Budget (104 dB) – Receiver Sensitivity -101 dBm – Programmable Output Power from -17 dBm ...
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Pin-out Diagram Figure 1-1. Note: AT86RF231 2 AT86RF231 Pin-out Diagram ...
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Pin Descriptions Table 1-1. Pin Description AT86RF231 Pins Name Type 1 DIG3 Digital output (Ground) 2 DIG4 Digital output (Ground) 3 AVSS Ground 4 RFP RF I/O 5 RFN RF I/O 6 AVSS Ground 7 DVSS Ground 8 /RST ...
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Table 1-1. Pin Description AT86RF231 (Continued) Pins Name Type 29 AVDD Supply 30 AVSS Ground 31 AVSS Ground 32 AVSS Ground Paddle AVSS Ground AT86RF231 4 Description Regulated 1.8V voltage regulator; analog domain, see Analog ground Analog ground Analog ground ...
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Analog and RF Pins 1.2.1 Supply and Ground Pins EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. ...
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The RF port DC values depend on the operating state, refer to page 33. In TRX_OFF state, when the analog front-end is disabled (see Clock State” on page In transmit mode, a control loop provides a common-mode voltage of 0.9V. ...
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Digital Pins The AT86RF231 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Interface” ...
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Register Description Register 0x03 (TRX_CTRL_0): The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM clock rate. Bit 7 6 PAD_IO Read/Write R/W R/W Initial Value 0 0 • Bit [7:6] - PAD_IO The ...
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Disclaimer Typical values contained in this datasheet are based on simulations and testing. Min and Max values are available when the radio transceiver has been fully characterized. 3. Overview The AT86RF231 is a feature rich, low-power 2.4 GHz radio ...
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General Circuit Description This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodula- tion including time and frequency synchronization and data buffering. The number ...
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An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the SPI interface and additional control ...
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Application Circuits 5.1 Basic Application Schematic A basic application schematic of the AT86RF231 with a single-ended RF connector is shown in Figure 5-1 on page RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling ...
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Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes, refer to Crosstalk from ...
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Extended Feature Set Application Schematic The AT86RF231 supports additional features like: • • • • • An extended feature set application schematic illustrating the use of the AT86RF231 Extended Feature Set, see ure 5-2 on page is possible to ...
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DIG1/DIG2, the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1). During transmit the AT86RF231 TX signal is amplified using an external PA (N1) and ...
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Microcontroller Interface This section describes the AT86RF231 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see are described below. Figure 6-1. Microcontrollers with a master SPI such as Atmel's AVR family interface directly to ...
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Table 6-1. SLP_TR /RST DIG2 6.1 SPI Timing Description Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise ...
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The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one ...
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SPI Protocol Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 6-2 on page additional mode-dependent information. Table 6-2. SPI Command Byte definition Bit 7 Bit 6 Bit 5 Bit 4 ...
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Figure 6-5. Each register access must be terminated by setting /SEL = H. Figure 6-6 on page 20 and read respectively. Figure 6-6. Example SPI Sequence - Register Access Mode Register Write Access /SEL SCLK MOSI WRITE COMMAND MISO PHY_STATUS ...
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Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e.g. after reading the PHR byte only. On Frame Buffer write access the second byte transferred on MOSI contains the ...
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Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU /SEL SCLK MOSI COMMAND MISO PHY_STATUS XX Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For ...
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On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see On SRAM read or write accesses do not attempt to read or write bytes beyond ...
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Radio Transceiver Status information Each SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status ...
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Radio Transceiver Identification The AT86RF231 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID. 6.4.1 Register Description - AT86RF231 Identification ...
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Table 6-6. Register Bit MAN_ID_0 Register 0x1F (MAN_ID_1): Bit +0x1F Read/Write Reset Value • Bit [7:0] - MAN_ID_1 Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). ...
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Sleep/Wake-up and Transmit Signal (SLP_TR) Pin 11 (SLP_TR multi-functional pin. Its function relates to the current state of the AT86RF231 and is summarized in explained in detail Table 6-8. SLP_TR Multi-functional Pin Transceiver Status Function PLL_ON TX ...
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Figure 6-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer SLP_TR CLKM 35 CLKM clock cycles Note: Timing figure t RX_ON and RX_AACK_ON states For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master ...
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Interrupt Logic 6.6.1 Overview The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending ...
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Note that AWAKE_END interrupt can usually not be seen when the transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all inter- rupts. In this case, state TRX_OFF is normally entered before the microcontroller could ...
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Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN Read/Write R/W R/W Reset Value 0 0 • Bit 7 - PA_EXT_EN ...
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Bit 0 - IRQ_POLARITY The default polarity of the IRQ pin is active high. The polarity can be configured to active low via register bit IRQ_POLARITY, see Table 6-11. Register Bit IRQ_POLARITY This setting does not affect the polarity ...
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Operating Modes 7.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the AT86RF231, such as receiving and transmitting frames, the power up sequence and sleep. The Basic Operating Mode is designed for IEEE ...
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A successful state change can be verified by reading the radio transceiver status from register 0x01 (TRX_STATUS). If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF231 state transition. Do not try to initiate a further state ...
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All digital inputs have pull-up or pull-down resistors during P_ON state, refer to “Pull-Up and Pull-Down Configuration” on page where GPIO signals are floating after power on or reset. The input pull-up and pull-down resis- tors are disabled when the ...
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Entering the TRX_OFF state from P_ON, SLEEP, or RESET state is indicated by interrupt IRQ_4 (AWAKE_END). 7.1.2.4 PLL_ON - PLL State Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has ...
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This state can only be entered by setting pin 11 (SLP_TR while the radio transceiver is in the RX_ON state, refer to State” on page SLP_TR pin, see down sequence. Note that for CLKM clock rates 250 kHz ...
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A reset forces the radio transceiver into TRX_OFF state. If the device is still in the P_ON state it remains in the P_ON state though. A reset is initiated with pin /RST = L and the state is left after ...
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Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode -16 0 TRX_STATE PLL_ON SLP_TR IRQ Typ. Processing Delay 16 µs Number of Octets Frame Content TRX_STATE IRQ Interrupt latency 7.1.4 Basic Operating Mode Timing The following ...
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Wake-up Procedure The wake-up procedure from SLEEP state is shown in Figure 7-4. Event State Block Time The radio transceivers SLEEP state is left by releasing pin SLP_TR to logic low. This restarts the XOSC and DVREG. After t ...
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BUSY_TX and RX_ON States The transition from PLL_ON to BUSY_TX state and subsequent to RX_ON state is shown in Figure 7-6 on page Figure 7-6. Pin State Block Command Time Starting from PLL_ON state it is further assumed that ...
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L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (reg- ister 0x03, TRX_CTRL_0), refer to 117. After releasing the reset pin (/RST = H) the wake-up sequence including an FTN calibration cycle is performed, ...
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Table 7-1. State Transition Timing (Continued) No Symbol Transition ⇒ PLL_ON TR10 ⇒ BUSY_TX TR11 ⇒ All modes TR12 ⇒ RESET TR13 Various ⇒ TR14 States The state transition timing ...
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Register Description Register 0x01 (TRX_STATUS): A read access to TRX_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively a state transition ...
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Table 7-3. Register Bits TRX_STATUS Notes: 8111A–AVR–05/08 Radio Transceiver Status, Register Bits TRX_STATUS Value State Description 0x00 P_ON 0x01 BUSY_RX 0x02 BUSY_TX 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) (3) 0x0F SLEEP (1) 0x11 BUSY_RX_AACK (1) 0x12 BUSY_TX_ARET ...
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Register 0x02 (TRX_STATE): The radio transceiver states are controlled via register bits TRX_CMD, which receives the state transition commands. This register is used for Basic and Extended Operating Mode, refer to Operating Mode” on page Bit 7 6 +0x02 TRAC_STATUS ...
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Extended Operating Mode The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks, requested by the IEEE 802.15.4 standard, by ...
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Figure 7-8. Extended Operating Mode State Diagram (Power-on after V FORCE_TRX_OFF (all modes except SLEEP) SHR Detected BUSY_RX (Receive State) Frame End RX_ON_NOCLK (Rx Listen State) CLKM=OFF SHR Detected BUSY_RX_AACK Trans- action Finished SHR Detected BUSY_RX_ AACK_NOCLK Frame CLKM=OFF Rejected ...
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State Control The Extended Operating Mode states RX_AACK and TX_ARET are controlled via register bits TRX_CMD (register 0x02, TRX_STATE), which receives the state transition commands. The states are entered from TRX_OFF or PLL_ON state as illustrated by completion of ...
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Configuration The use of the Extended Operating Mode is based on Basic Operating Mode functionality. Only features beyond the basic radio transceiver functionality are described in the following sections. For details on the Basic Operating Mode refer to 33. ...
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The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in theAT86RF231. The MAX_BE and MIN_BE register bits (register 0x2F) sets the maximum and minimum CSMA back-off exponent (according to [1]). 7.2.3 ...
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The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see 68. During the operations described above the AT86RF231 remains in BUSY_RX_AACK state. AT86RF231 52 Section 7.2.7 “Register Description - Control Registers” on page 8111A–AVR–05/08 ...
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Figure 7-9. Flow Diagram of RX_AACK Note 1: Address match, Promiscuous Mode and Reserved Frames radio transceiver in Promiscuous Mode, or configured to receive Reserved Frames handles received frames passing the third level of filtering - For details ...
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Description of RX_AACK Configuration Bits Overview Table 7-5 on page 54 transaction. For address filtering it is further required to setup address registers to match to the expected address. Configuration and address bits are to be set in TRX_OFF ...
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OQPSK_DATA_RATE • SFD_VALUE • ANT_DIV • RX_PDT_LEVEL are completely independent from RX_AACK mode. Each of these operating modes can be com- bined with the RX_AACK mode. 7.2.3.2 Configuration of IEEE Scenarios Normal Device Table 7-6 on page 55 ating ...
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The same holds for PAN coordinators, see PAN-Coordinator Table 7-7. Register Address 0x20,0x21 0x22,0x23 0x24, ........... 0x2B 0x0C 0x2C 0x2E 0x2E 0x2E Promiscuous Mode The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.2. This mode is fur- ...
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Only second level filter rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, are applied to the received frame. Table 7-8 on page 57 Table 7-8. Register Address 0x20,0x21 0x22,0x23 0x24, ... 0x2B 0x17 0x2E 0x2E If the radio transceiver is ...
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Configuration of non IEEE 802.15.4 Compliant Scenarios Sniffer Table 7-9 on page 58 RX_AACK configuration bits, refer to All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END). After frame reception register bit RX_CRC_VALID (register 0x06, PHY_RSSI) ...
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Table 7-10. 0x2E 0x2E 0x2E There are two different options for handling reserved frame types. 1. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address ...
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Short Acknowledgment Frame (ACK) Start Timing Register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1), see defines the symbol time between frame reception and transmission of an acknowledgment frame. Table 7-11. Register Address 0x17 Note that this feature can be used in all ...
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Frame Filtering Frame Filtering is an evaluation whether or not a received frame is dedicated for this node. To accept a received frame and to generate an address match interrupt IRQ_5 (AMI) a filtering pro- cedure as described in ...
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RX_AACK Slotted Operation - Slotted Acknowledgement AT86RF231 supports slotted acknowledgement operation, refer to IEEE 802.15.4-2006, section 5.5.4.1, in conjunction with the microcontroller. In RX_AACK mode with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set, the transmission of an acknowledgement frame ...
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Figure 7-11. Example Timing of an RX_AACK Transaction 0 64 Frame Type TRX_STATE RX_AACK_ON RX/TX IRQ Typ. Processing Delay If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame is sent already 2 symbol times after the reception ...
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TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry Figure 7-12. Flow Diagram of TX_ARET AT86RF231 64 TRX_STATE = TX_ARET_ON frame_rctr = 0 N Start TX Y TRX_STATE = BUSY_TX_ARET TRAC_STATUS = INVALID (see Note 1) Note 1: If ...
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Overview The implemented TX_ARET algorithm is shown in In TX_ARET mode, the AT86RF231 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4-2006, section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted ...
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Table 7-12. Value Note that if no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues IRQ_3 (TRX_END) directly after the frame transmission has been ...
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TRAC_STATUS = SUCCESS_DATA_PENDING if the frame pending subfield of the received ACK frame was set to 1. 7.2.5 Interrupt Handling The interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to setting the ...
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Register Summary The following registers are to be configured to control the Extended Operating Mode: Table 7-14. Reg.-Addr 0x01 0x02 0x04 0x08 0x09 0x17 0x20 - 0x2B 0x2C 0x2D 0x2E 0x2F 7.2.7 Register Description - Control Registers Register 0x01 ...
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Table 7-15. Register Bit TRX_STATUS Notes: Register 0x02 (TRX_STATE): The AT86RF231 radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. A ...
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Section 7.2.3 “RX_AACK_ON - Receive with Automatic ACK” on page 51 “TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry” on page Table 7-16. Register Bits TRAC_STATUS Notes: TX_ARET SUCCESS_DATA_PENDING: RX_AACK SUCCESS_WAIT_FOR_ACK: • Bit [4:0] - TRX_CMD A write access ...
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Note: Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON Read/Write R/W R/W Reset Value 0 0 • Bit 7 ...
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If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as speci- fied in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4, section 7.2.1.1.1. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked ...
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Register 0x2C (XAH_CTRL_0): Register 0x2C (XAH_CTRL_0 control register for Extended Operating Mode. Bit 7 6 +0x2C MAX_FRAME_RETRIES Read/Write R/W R/W Reset Value 0 0 • Bit [7:4] - MAX_FRAME_RETRIES The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the ...
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Bit [7:0] - CSMA_SEED_0 This register contains the lower 8 bit of the CSMA_SEED, bits [7:0]. The higher 3 bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that ...
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MAC command frame is actually a data request command or not. • Bit 4 - AACK_ DIS_ACK If this bit is set ...
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Register Description - Address Registers Register 0x20 (SHORT_ADDR_0): This register contains the lower 8 bit of the MAC short address for Frame Filter address recogni- tion, bits [7:0]. Bit +0x20 Read/Write Reset Value Register 0x21 (SHORT_ADDR_1): This register contains ...
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Register 0x24 (IEEE_ADDR_0): This register contains the lower 8 bit of the MAC IEEE address for Frame Filter address recogni- tion, bits [7:0]. Bit +0x24 Read/Write Reset Value Register 0x25 (IEEE_ADDR_1): This register contains 8 bit of the MAC IEEE ...
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Register 0x28 (IEEE_ADDR_4): This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [39:32]. Bit +0x28 Read/Write Reset Value Register 0x29 (IEEE_ADDR_5): This register contains 8 bit of the MAC IEEE address for Frame ...
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Functional Description 8.1 Introduction - IEEE 802.15.4 - 2006 Frame Format Figure 8-1 on page 79 defined by IEEE 802.15.4. access control (MAC) layer. Figure 8-1. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU) Preamble Sequence 5 octets ...
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Received frames with a frame length field set to 0x00 (invalid PHR) are not signaled to the microcontroller. Table 8-1 on page 80 Table 8-1. 8.1.2 MAC Protocol Layer Data Unit (MPDU) Figure 8-2 on page 80 Figure 8-2. IEEE ...
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Bit [2:0]: describe the frame type. 802.15.4, section 7.2.1.1.1. Table 8-2. Frame Control Field Bit Assignments Frame Type Value 100 - 111 This subfield is used for address filtering by the third level filter rules. Only frame types 0 ...
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Bit 6: The "Intra-PAN" subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address field is omitted. In RX_AACK mode, this bit is evaluated by the address filter ...
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Bit [15:14]: the "Source Addressing Mode" subfield, with similar meaning as "Destination Addressing Mode", see Table 8-3 on page The subfields of the FCF (Bits 0- 10-15) affect the address filter logic of the AT86RF231 while operating ...
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Auxiliary Security Header Field The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB ...
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Frame Check Sequence (FCS) The Frame Check Sequence (FCS) is characterized by: • Indicate bit errors, based on a cyclic redundancy check (CRC) of length 16 bit • Uses International Telecommunication Union (ITU) CRC polynomial • Automatically evaluated during ...
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Automatic FCS generation The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1 (reset value). This allows the AT86RF231 to compute the FCS autonomously. For a frame with a frame length specified ≤ N ...
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Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN Read/Write R/W R/W Reset Value 0 0 • Bit ...
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Bit 7 - RX_CRC_VALID Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is ...
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Received Signal Strength Indicator (RSSI) The Received Signal Strength Indicator is characterized by: • Minimum RSSI level is -90 dBm (RSSI_BASE_VAL) • Dynamic range • Minimum RSSI value is 0 • Maximum RSSI value is 28 ...
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Figure 8- -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 8.3.4 Register Description Register 0x06 (PHY_RSSI): Bit +0x06 Read/Write Reset Value • Bit 7 - RX_CRC_VALID Refer to register description in • Bit [6:5] - RND_VALUE ...
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Energy Detection (ED) The Energy Detection (ED) module is characterized by: • 85 unique energy levels defined • resolution 8.4.1 Overview The receiver ED measurement is used by the network layer as part of a channel selection ...
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Data Interpretation The PHY_ED_LEVEL is an 8-bit register. The ED value of the AT86RF231 has a valid range from 0x00 to 0x54 with a resolution of 1 dB. All other values do not occur; a value of 0xFF indi- ...
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Register Description Register 0x07 (PHY_ED_LEVEL): The ED_LEVEL register contains the result measurement. Bit +0x07 Read/Write Reset Value • Bit [7:0] - ED_LEVEL The minimum ED value (ED_LEVEL = 0) indicates receiver power less than or equal ...
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Clear Channel Assessment (CCA) The main features of the Clear Channel Assessment (CCA) module are: • All 4 modes are available as defined by IEEE 802.15.4-2006 in section 6.9.9 • Adjustable threshold for energy detection algorithm 8.5.1 Overview A ...
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Data Interpretation The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). Note, register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is ...
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Table 8- Note recommended to perform CCA measurements in RX_ON state only. To avoid switching accidentally to BUSY_RX state the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to receiver ...
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Register Description Register 0x01 (TRX_STATUS): Two register bits of register 0x01 (TRX_STATUS) signal the status of the CCA measurement. Bit 7 6 +0x01 CCA_DONE CCA_STATUS Read/Write R R Reset Value 0 0 • Bit 7 - CCA_DONE This register ...
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...
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Link Quality Indication (LQI) According to IEEE 802.15.4, the LQI measurement is a characterization of the strength and/or quality of a received packet. The measurement may be implemented using receiver ED, a sig- nal-to-noise ratio estimation combination ...
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LQI value. Since the packet error rate is a statistical value, the PER shown in “Conditional Packet Error Rate versus LQI” on page 99 tions. A reliable estimation of the packet error rate cannot be based on a single ...
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Module Description 9.1 Receiver (RX) 9.1.1 Overview The AT86RF231 receiver is split into an analog radio front end and a digital base band proces- sor (RX BBP), see Figure 9-1. RFP RFN The differential RF signal is amplified by ...
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Frame Receive Procedure The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in page 126. 9.1.3 Configuration In Basic Operating Mode the receiver is enabled by writing ...
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Register Description Register 0x15 (RX_SYN): This register controls the sensitivity threshold of the receiver. Bit 7 6 +0x15 RX_PDT_DIS R/W R Read/Write Reset Value 0 0 • Bit 7 - RX_PDT_DIS RX_PDT_DIS = 1 prevents the reception of a ...
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Transmitter (TX) 9.2.1 Overview The AT86RF231 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-2. DIG3/4 RFP RFN The TX BBP reads the frame data from the Frame Buffer ...
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Figure 9-3. TX Power Ramping 0 2 TRX_STATE PLL_ON SLP_TR PA buffer PA Modulation When using an external RF front-end (refer to may be required to adjust the startup time of the external PA relative to the internal building blocks ...
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Bit [5:4] - PA_LT These register bits control the enable lead time of the internal PA relative to the beginning of the transmitted frame. Table 9-3. Register Bits PA_LT • Bit [3:0] - TX_PWR These register bits determine the ...
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Frame Buffer The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI inter- face, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. ...
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User accessible Frame Content The AT86RF231 supports an IEEE 802.15.4 compliant frame format as shown in page 108. Figure 9-4. AT86RF231 Frame Structure Length [octets] 0 Frame Preamble Sequence Duration 4 octets / 128 µs SHR not accesible Access ...
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Interrupt Handling Access conflicts may occur when reading and writing data simultaneously at the two indepen- dent ports of the Frame Buffer, TX/RX BBP and SPI. Both of these ports have their own address counter that points to the ...
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Voltage Regulators (AVREG, DVREG) The main features of the Voltage Regulator blocks are: • Bandgap stabilized 1.8V supply for analog and digital domain • Low dropout (LDO) voltage regulator • Configurable for usage of external voltage regulator 9.4.1 Overview ...
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Register Description Register 0x10 (VREG_CTRL): This register controls the use of the voltage regulators and indicates the status of these. Bit 7 6 +0x10 AVREG_EXT AVDD_OK Read/Write R/W R Reset Value 0 0 • Bit 7 - AVREG_EXT If ...
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Bit 2 - DVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG_EXT = 1. Table 9-8. Register Bit DVDD_OK Note • While the reset ...
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Battery Monitor (BATMON) The main features of the battery monitor are: • Configurable voltage threshold range: 1.7V to 3.675V • Generates an interrupt when supply voltage drops below a threshold 9.5.1 Overview The battery monitor (BATMON) detects and indicates ...
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Interrupt Handling A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ_7 (BAT_LOW), see if BATMON_OK changes from interrupt is generated when: • The battery voltage is under the default ...
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Bit [3:0] - BATMON_VTH The threshold values for the battery monitor are set by register bits BATMON_VTH: Table 9-11. BATMON_VTH[3:0] 8111A–AVR–05/08 Battery Monitor Threshold Voltage Value Voltage [V] BATMON_HR = 1 0x0 2.550 0x1 2.625 0x2 2.700 0x3 2.775 ...
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Crystal Oscillator (XOSC) The main crystal oscillator features are: • 16 MHz amplitude controlled crystal oscillator • 215 µs typical settling time after leaving SLEEP state • Configurable trimming capacitance array • Configurable clock output (CLKM) 9.6.1 Overview The ...
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Additional internal trimming capacitors C 4.5 pF with a 0.3 pF resolution is selectable using XTAL_TRIM of register 0x12 (XOSC_CTRL). To calculate the total load capacitance, the following formula can be used C = 0 ...
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Note • During reset procedure, see CLKM_CTRL are shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM_CTRL delivers the reset value 1. For that reason it is recommended to write the previous ...
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Bit 3 - CLKM_SHA_SEL Register bit CLKM_SHA_SEL defines if a new clock rate, defined by CLKM_CTRL, is set imme- diately or after the next SLEEP cycle. Table 9-13. Register Bit CLKM_SHA_SEL • Bit [2:0] - CLKM_CTRL These register bits ...
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Bit [3:0] - XTAL_TRIM The register bits XTAL_TRIM control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 4 selectable with a resolution of 0.3 pF. ...
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Frequency Synthesizer (PLL) The main PLL features are: • Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels • Autonomous calibration loops for stable operation within the operating range • Two PLL-interrupts for status indication • Fast ...
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If the PLL operates for a long time on the same channel, e.g. more than 5 min, or the operating temperature changes significantly recommended to initiate the calibration loops manually. Both calibration loops can be initiated manually by ...
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Table 9-17. Register Bit CHANNEL Register 0x1A (PLL_CF): This register controls the operation of the center frequency calibration loop. Bit 7 6 +0x1A PLL_CF_START Read/Write R/W R/W Reset Value 0 1 • Bit 7 - PLL_CF_START PLL_CF_START = 1 initiates ...
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Bit 7 - PLL_DCU_START PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after at most t ing the calibration. • Bit [6:0] - Reserved AT86RF231 124 = 6 µs, the register bit is set ...
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Automatic Filter Tuning (FTN) 9.8.1 Overview The FTN is incorporated to compensate device tolerances for temperature, supply voltage varia- tions as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband ...
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Radio Transceiver Usage This section describes basic procedures to receive and transmit frames using the AT86RF231. For a detailed programming description refer to reference [6]. 10.1 Frame Receive Procedure A frame reception comprises of two actions: The PHY listens ...
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Frame Transmit Procedure A frame transmission comprises of two actions, a Frame Buffer write access and the transmis- sion of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. Figure 10-2 ...
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AT86RF231 Extended Feature Set 11.1 Security Module (AES) The security module (AES) is characterized by: • Hardware accelerated encryption and decryption • Compatible with AES-128 standard (128 bit key and data block size) • ECB (encryption/decryption) mode and CBC ...
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The encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM address 0x83, AES_CON or the mirrored version with SRAM address 0x94, AES_CON_MIRROR). The AES module control registers are only accessible using SRAM read and write accesses on ...
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A security operation can be started within one SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CON_MIRROR) to the SPI sequence. Register AES_CON_MIRROR is a mirrored version of register 0x83 (AES_CON). Figure 11-1. ECB Programming SPI ...
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When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. This last round key is the content of ...
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Note that IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only implements a one-way hash function. 11.1.5 Data Transfer - Fast SRAM Access The ECB and CBC modules including the AES core are clocked with 16 MHz. ...
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Start of Security Operation and Status A security operation is started within one SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CON_MIRROR) to the SPI sequence. Register AES_CON_MIRROR is a mirrored version of register 0x83 ...
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Table 11-3. Register Bit AES_ER • Bit [6:1] -Reserved • Bit 0 - AES_RY Table 11-4. Register Bit AES_RY Register 0x83 (AES_CON): This register controls the operation of the security module. Do not access this register during AES operation to ...
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Bits 3 - AES_DIR This register bit sets the AES operation direction, either encryption or decryption. Table 11-7. Register Bit AES_DIR • Bit [2:0] - Reserved Register 0x94 (AES_CON_MIRROR): Register 0x94 is a mirrored version of register 0x83 (AES_CON), ...
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Random Number Generator 11.2.1 Overview The AT86RF231 incorporates a 2-bit truly random number generator by observation of noise. This random number can be used to: • Generate random seeds for CSMA-CA algorithm • Generate random values for AES key ...
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High Data Rate Modes The main features are: • High Data Rate Transmission Mb/s. • Support of Basic and Extended Operating Mode • Support of other features of the Extended Feature Set 11.3.1 Overview The AT86RF231 ...
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Figure 11-6. High Data Rate Frame Structure 0 192 512 250 kb/s PSDU: 80 octets 500 kb/s PSDU: 80 octets 1000 kb/s PSDU: 80 octets 2000 kb/s PSDU: 80 octets Due to the overhead caused by the SHR, PHR as ...
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Figure 11-8 on page 139 access. Figure 11-8. Packet Structure - High Data Rate Frame Buffer Read Access byte 1 (command byte) MOSI reserved[5:0] MISO PHY_STATUS 11.3.4 High Data Rate Energy Detection According to IEEE 802.15.4 the ...
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Figure 11-9. High Data Rate AACK Timing 0 AACK_ACK_TIME = 0 AACK_ACK_TIME = 1 If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set the acknowledgment time is reduced from 192 µ µs. 11.3.6 Register Description Register 0x0C (TRX_CTRL_2): ...
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Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for various RX_AACK settings. Bit 7 6 +0x17 Reserved AACK_FLTR_RES_FT Read/Write R/W R Reset Value 0 0 • Bit [7:6] - Reserved • Bit 5 - AACK_FLTR_RES_FT Refer to ...
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Antenna Diversity The Antenna Diversity implementation is characterized by: • Improves signal path robustness between nodes • AT86RF231 self-contained antenna diversity algorithm • Direct register based antenna selection 11.4.1 Overview Due to multipath propagation effects between network nodes, the ...
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Generally, the Antenna Diversity algorithm is enabled with register bit ANT_DIV_EN (register 0x0D, ANT_DIV) set. In this case the control of an antenna diversity switch must be enabled by register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). The internal connection to digital ...
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Bit [3:0] - PDT_THRES These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled, the value shall be set to PDT_THRES = 3, otherwise it shall be set back to the ...
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Table 11-12. Antenna Diversity Control Register Bit ANT_DIV_EN Note: • Bit 2 - ANT_EXT_SW_EN If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control signal for an Antenna Diversity switch. The selection of ...
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Table 11-14. Antenna Diversity Switch Control Register Bit ANT_CTRL Note: AT86RF231 146 Value Description 0 Reserved 1 Antenna 1 DIG1 = H DIG2 = L 2 Antenna 0 DIG1 = L DIG2 = H 3 Default value for ANT_EXT_SW_EN = ...
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RX/TX Indicator The main features are: • RX/TX Indicator to control an external RF Front-End • Microcontroller independent RF Front-End Control • Provide TX Timing Information 11.5.1 Overview While IEEE 802.15 low cost, low power standard, solutions ...
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The modulation starts 16 µs after the rising edge of SLP_TR. During this time, the PA buffer and the internal PA are enabled. The control of an external PA is done via differential ...
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Bit 1 - IRQ_MASK_MODE Refer to • Bit 0 - IRQ_POLARITY Refer to 8111A–AVR–05/08 Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AT86RF231 29. 29. 149 ...
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RX Frame Time Stamping 11.6.1 Overview To determine the exact timing of an incoming frame, e.g. for beaconing networks, the reception of this frame can be signaled to the microcontroller via pin 10 (DIG2). The pin turns from L ...
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Register Description Register 0x04 (TRX_CTRL_1): Register 0x04 (TRX_CTRL_1 multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON Read/Write R/W R/W Reset Value 0 0 • ...
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Frame Buffer Empty Indicator 11.7.1 Overview For time critical applications that want to start reading the frame data as early as possible, the Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates ...
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Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON Read/Write R/W R/W Reset Value 0 0 • ...
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Dynamic Frame Buffer Protection 11.8.1 Overview The AT86RF231 continues the reception of incoming frames as long any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will ...
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Bit [1:0] - OQPSK_DATA_RATE Refer to 11.9 Configurable Start-Of-Frame Delimiter 11.9.1 Overview The SFD is a field indicating the end of the SHR and the start of the packet data. The length of the SFD is 1 octet (2 ...
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Electrical Characteristics 12.1 Absolute Maximum Ratings Note: . Table 12-1. Absolute Maximum Ratings No. Symbol Parameter 12.1.1 T Storage temperature STOR 12.1.2 T Lead temperature LEAD 12.1.3 V ESD robustness ESD 12.1.4 P Input RF level RF 12.1.5 V ...
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Digital Pin Characteristics .Test Conditions: T Table 12-3. Digital Pin Characteristics No. Symbol Parameter 12.3.1 V High level input voltage IH 12.3.2 V Low level input voltage IL 12.3.3 V High level output voltage OH 12.3.4 V Low level ...
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Table 12-4. Digital Interface Timing Characteristics (Continued) 12.4.15 t AES core cycle time 12 12.4.16 t Interrupt event latency IRQ 12.4.17 f Clock frequency at pin 17 (CLKM) CLKM Notes: 1. Maximum pulse width less than (TX frame length + ...
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Transmitter Characteristics Test Conditions (unless otherwise stated 3.0V Table 12-6. Transmitter Characteristics No. Symbol Parameter 12.6 Output power TX 12.6.2 P Output power range RANGE 12.6.3 P Output power tolerance ACC 12.6.4 TX ...
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Receiver Characteristics Test Conditions (unless otherwise stated 3.0V ure 5-1 on page Table 12-7. Receiver Characteristics No. Symbol Parameter 12.7.1 P Receiver sensitivity SENS 250 kb/s 500 kb/s 1000 kb/s 2000 kb/s Antenna Diversity 12.7.2 ...
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Current Consumption Specifications Test Conditions (unless otherwise stated 3.0V Table 12-8. Current Consumption Specifications No. Symbol Parameter 12.8.1 I Supply current transmit state BUSY_TX 12.8.2 I Supply current RX_ON state RX_ON 12.8.3 I Supply current ...
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Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The ...
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PLL_ON state Figure 13-2. Current Consumption in PLL_ON State 7.0 6.5 6.0 5.5 5.0 4.5 4.0 13.1.3 RX_ON state Figure 13-3. Current Consumption in RX_ON State 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 8111A–AVR–05/08 Current Consumption ...
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TX_BUSY state Figure 13-4. Current Consumption in RX_BUSY State 16.0 15.0 14.0 13.0 12.0 11.0 13.2 State Transition Timing Figure 13-5. Transition Time from EVDD to P_ON (CLKM available) 500 450 400 350 300 250 200 150 100 50 ...
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Figure 13-6. Transition Time from SLEEP to TRX_OFF (AWAKE_END) 500 450 400 350 300 250 200 150 100 50 0 Figure 13-7. Transition Time from TRX_OFF to PLL_ON 140 120 100 8111A–AVR–05/08 Transition Time from ...
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Register Summary The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: Addr Name Bit7 Bit6 0x00 - - - 0x01 TRX_STATUS CCA_DONE CCA_STATUS 0x02 TRX_STATE TRAC_STATUS[1] TRAC_STATUS[0] 0x03 ...
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CSMA_SEED_0 CSMA_SEED_0[7] CSMA_SEED_0[6] 0x2E CSMA_SEED_1 AACK_FVN_MODE[1] AACK_FVN_MODE[0] 0x2F CSMA_BE MAX_BE[3] MAX_BE[2] .... - - The reset values of the AT86RF231 registers in state P_ON page 167. Note: Table 14-1. Register Summary - Reset Values Address Reset Value Address 0x00 ...
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Abbreviations AACK ACK ADC AD AGC AES ARET AVREG AWGN BATMON BBP BPF CBC CRC CCA CSMA-CA CW DVREG ECB ED ESD EVM FCF FCS FIFO FTN GPIO ISM LDO LNA LO LQI LSB MAC MFR AT86RF231 168 - ...
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MHR MISO MOSI MSB MSDU MPDU MSK O-QPSK PA PAN PCB PER PHR PHY PLL POR PPF PRBS PSDU PSD QFN RF RSSI RX SCLK /SEL SFD SHR SPI SRAM SSBF TX VCO VREG XOSC 8111A–AVR–05/08 - MAC header - ...
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Ordering Information Ordering Code Package AT86RF231-ZU QN Package Type Description QN 32QN2, 32 lead 5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: 17. Soldering Information Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. 18. ...
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Package Drawing - 32QN2 E Top View Top View E2 E2 Bottom View Bottom View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-6, for proper dimensions, tolerances, datums, etc. 2. Dimension ...
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Appendix A - Continuous Transmission Test Mode 20.1 Overview The AT86RF231 offers a Continuous Transmission Test Mode to support final application / pro- duction tests as well as certification tests. Using this test mode the radio transceiver transmits continuously ...
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Note: The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral ...
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Register Description Register 0x36 (TST_CTRL_DIGI): Register TST_CTRL_DIG enables the continuous transmission test mode. Bit 7 6 +0x36 Reserved Read/Write R/W R/W Reset Value 0 0 • Bit [7:4] - Reserved • Bit [3:0] - TST_CTRL_DIG These register bits enable ...
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Appendix B - Errata 21.1 AT86RF231 Rev.A No known errata 8111A–AVR–05/08 AT86RF231 175 ...
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References [1] [2] [3] [4] [5] [6] AT86RF231 176 IEEE Std 802.15.4™-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) and Physical Layer ...
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Table of Contents Features ..................................................................................................... 1 1 Pin-out Diagram ....................................................................................... 2 1.1 Pin Descriptions .................................................................................................3 1.2 Analog and RF Pins ...........................................................................................5 1.3 Digital Pins .........................................................................................................7 2 Disclaimer ................................................................................................. 9 3 Overview ................................................................................................... 9 4 General Circuit Description ................................................................... 10 5 ...
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Frame Buffer ..................................................................................................107 9.4 Voltage Regulators (AVREG, DVREG) .........................................................110 9.5 Battery Monitor (BATMON) ...........................................................................113 9.6 Crystal Oscillator (XOSC) ..............................................................................116 9.7 Frequency Synthesizer (PLL) ........................................................................121 9.8 Automatic Filter Tuning (FTN) .......................................................................125 10 Radio Transceiver Usage .................................................................... 126 10.1 Frame Receive ...
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Ordering Information ........................................................................... 170 17 Soldering Information .......................................................................... 170 18 Package Thermal Properties ............................................................... 170 19 Package Drawing - 32QN2 ................................................................... 171 20 Appendix A - Continuous Transmission Test Mode ......................... 172 20.1 Overview ........................................................................................................172 20.2 Configuration .................................................................................................172 20.3 ...
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