ADE7751 Analog Devices, ADE7751 Datasheet
ADE7751
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ADE7751 Summary of contents
Page 1
... The ADE7751 will remain in a reset condition DD until the supply voltage on AV below 4 V, the ADE7751 will also be reset and no pulses will be issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are matched whether the HPF in Channel off ...
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... ADE7751–SPECIFICATIONS Parameter 3 ACCURACY 1 Measurement Error on Channels 1 and 2 Gain = 1 Gain = 2 Gain = 8 Gain = 16 1 Phase Error between Channels V1 Phase Lead 37 (PF = 0.8 Capacitive) V1 Phase Lag 60 (PF = 0.5 Inductive Power Supply Rejection Output Frequency Variation (CF Power Supply Rejection Output Frequency Variation (CF FAULT DETECTION Fault Detection Threshold Inactive i/p < ...
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... Figure 1. Timing Diagram for Frequency Outputs –3– Test Conditions/Comments F1 and F2 Pulsewidth (Logic Low) Output Pulse Period. See Transfer Function section. Time Between F1 Falling Edge and F2 Falling Edge CF Pulsewidth (Logic High) CF Pulse Period. See Transfer Function section. Minimum Time Between F1 and F2 Pulse ADE7751 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7751 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... V can also be sustained on these inputs without risk of permanent damage. RESET 9 Reset Pin for the ADE7751. A logic low on this pin will hold the ADCs and digital circuitry in a reset condition. Bringing this pin logic low will clear the ADE7751 internal registers. 10 REF Provides Access to the On-Chip Voltage Reference ...
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... CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or by the gate oscillator circuit. 19 FAULT This logic output will go active high when a fault condition occurs ...
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... TPC 5. Error Reading (PF = 0.5, Gain = 1) 0. 0.5 GAIN = 2 ON-CHIP REFERENCE 0.20 +85 C 0.10 0.00 –0.10 –40 C –0.20 –0.30 10 100 0.01 TPC 6. Error Reading (Gain = 2) –7– ADE7751 + + – 0 AMPS + 0.5 – 0.5 + 0 AMPS + 0 0.5 – ...
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... PRELIMINARY TECHNICAL DATA ADE7751 0.20 +25 C PF=1 0.10 0.00 +85 C PF=0.5 –0.10 –0.20 +25 C PF=0.5 –0.30 –0.40 –0. 0.5 GAIN = 8 ON-CHIP REFERENCE –0.60 0.01 0.1 1 AMPS TPC 7. Error Reading (PF = 0.5, Gain = 8) 0. 0.5 GAIN = 16 0.40 ON-CHIP REFERENCE 0.20 0.00 + 0.5 –0.20 –0.40 –0.60 – 0.5 –0.80 –1.00 0.01 0.1 1 AMPS TPC 8. Error Reading (Gain = 16) ...
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... MEAN: 0.47494 STD DEV: 1.71819 GAIN = 16 TEMP = 25 C –15 –10 – 100nF 100nF AC/ V1A F1 33nF ADE7751 CF V1B 33nF REVP V1N 1k FAULT 33nF CLKOUT Y1 22pF V2N 33nF 3.58MHz CLKIN 22pF G0 GAIN V2P 33nF SELECT G1 S0 ...
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... TIME Figure 2. Signal Processing Block Diagram The low-frequency output of the ADE7751 is generated by accumulating this real power information. This low frequency inherently means a long accumulation time between output pulses. The output frequency is therefore proportional to the average real power. This average real power information can in turn be accumulated (e ...
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... ANALOG INPUTS Channel V2 (Voltage Channel) The output of the line voltage transducer is connected to the ADE7751 at this analog input. Channel fully differen- tial voltage input. The maximum peak differential signal on Channel 2 is 660 mV. Figure 4 illustrates the maximum signal levels that can be connected to the ADE7751 Channel 2. ...
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... Figure 7 shows two typical connections for Channel V2. The first option uses a PT (potential transformer) to provide complete isola- tion from the mains voltage. In the second option, the ADE7751 is biased around the neutral wire and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. ...
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... V1B on power-up, the fault indicator (FAULT) will go active after about one second. In addition, if V1B is greater than V1A the ADE7751 will select V1B as the input. The fault detection is automatically disabled when the voltage signal on Channel 1 is less than 0.5% of the full-scale input range. This will eliminate false detection of a fault due to noise at light loads ...
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... B TEST CURRENT TRANSFER FUNCTION Frequency Outputs F1 and F2 The ADE7751 calculates the product of two voltage signals (on Channel 1 and Channel 2) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is FILTER FAULT output on F1 and F2 in the form of active low pulses ...
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... F1 and F2 when both analog 2.72 inputs are half scale. The frequencies listed in Table VI align very well with those listed in Table V for maximum load. frequency 1– –15– ADE7751 Table IV Max for AC Signals 1–4 S0 (Hz) (Hz) 0 1.7 128 F1 43. ...
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... The ADE7751 also includes a “no load threshold” and “start- up current” feature that will eliminate any creep effects in the meter. The ADE7751 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2 ...