SAK C167CS-4RM-CA+ Infineon Technologies, SAK C167CS-4RM-CA+ Datasheet - Page 79

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SAK C167CS-4RM-CA+

Manufacturer Part Number
SAK C167CS-4RM-CA+
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAK C167CS-4RM-CA+

Packages
PG-MQFP-144
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
11.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
24
Program Memory
32.0 KByte
External XRAM Access
If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed
(during hold states) by an external master like an asynchronous SRAM.
Table 21
Parameter
Address setup time before RD/WR falling edge
Address hold time after RD/WR rising edge
Data turn on delay after RD falling edge
Data output valid delay after address latched
Data turn off delay after RD rising edge
Write data setup time before WR rising edge
Write data hold time after WR rising edge
WR pulse width
WR signal recovery time
Figure 24
Data Sheet
Address
Command
(RD, WR)
Write Data
Read Data
XRAM Access Timing (Operating Conditions apply)
External Access to the XRAM
t
40
t
42
t
43
75
t
47
Symbol
t
t
t
t
t
t
t
t
t
40
41
42
43
44
45
46
47
48
t
45
CC 2
CC –
CC 0
SR 4
SR 0
SR 10
SR 1
SR 18
SR
t
46
t
41
min.
t
t
40
44
t
Limit Values
48
max.
37
10
C167CS-4R
MCT04423
V2.2, 2001-08
C167CS-L
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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