TLE 8201R Infineon Technologies, TLE 8201R Datasheet - Page 20

• Manufacturer Part Number: TLE 8201R
• Manufacturer: Infineon Technologies

Specifications of TLE 8201R

• Packages: PG-DSO-36
• Ipeak: 8.0 A peak for OUT 1.2 ; 6.25 A peak for OUT 7
• Inhibit: Y
• Iq (typ): 0.2 µA2.5 µA
• Mounting: SMT
• Technology: BCD

4.3.4
The SPI is using a standard shift-register concept with daisy-chain capability. Any data
transmitted to the SPI will be available to the internal logic part at the end of the SPI
transmission (CSN L -> H). To read a specific register, the address of the register is sent
by the master to the SPI in a first SPI frame. The data that corresponds to this address
is transmitted by the SPI DO during the following (second) SPI frame to the master. The
default address for Status Register transmission after Power-ON Reset is 00.
The Status-Register-Reset command-bit is executed after the next SPI transmission.
The three bits RA_0, RA_1 and SRR act as command to read and reset (or not reset)
the addressed Status-Register. This is also explained in
The TSD status bit is not part of the adressable data but of the address independent
data. When any of the status registers is reset, the TSD bit is reset, too.
Figure 5
Data Sheet Rev. 2.0
Com-
ment
CSN
SO
SI
After Power-ON Reset, Status
Register 00 is sent by default
Status Register Address selection and Reset
x x x x x
x x x x x
Status Register Addressing and Reset
0
x
0
x
1
x
Status Register 01 is transferred to
SPI master, but not reset after
x x x x x
x x x x x
transmission
20
1
x
1
x
0
x
Status Register 10 is transferred to
SPI master, and reset after
Figure
x x x x x
x x x x x
transmission
5.
0
x
1
x
1
x
StatReg10 is reset
TLE 8201R
after CSN
2006-06-07
L->H
t