IR3895MTRPBF International Rectifier, IR3895MTRPBF Datasheet - Page 18
IR3895MTRPBF
Manufacturer Part Number
IR3895MTRPBF
Description
16A Highly Integrated Single-Input Voltage, Synchronous Buck Regulator in a PQFN package.
Manufacturer
International Rectifier
Datasheet
1.IR3895MTR1PBF.pdf
(42 pages)
Specifications of IR3895MTRPBF
Part Status
Active and Preferred
Package
PQFN / 5 x 6
Circuit
Single Output
Iout (a)
16
Switch Freq (khz)
0 - 1500
Input Range (v)
1.0 - 16
Output Range (v)
0.5 - 12
Pbf
PbF Option Available
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IR3895MTRPBF
Manufacturer:
IR
Quantity:
20 000
Figure 5b: Recommended startup for sequencing operation
Figure 5a: Recommended startup for Normal operation
memory tracking operation (Vtt‐DDR)
Figure 5c: Recommended startup for
18
(ratiometric or simultaneous)
FEBRUARY 01, 2012 | DATA SHEET| Rev 3.0
Vref=0
Pvin (12V)
Pvin (12V)
Intl_SS
Vcc
Vcc
Pvin(12V)
Single‐Input Voltage, Synchronous Buck Regulator
Enable >1.2V
Enable > 1. 2 V
Enable > 1. 2 V
Vcc
Vp>1V
Intl_SS
Intl_SS
Vp
Vp
- 18 -P
16A Highly Integrated SupIRBuck
Figure 5a shows the recommended start‐up sequence for
the normal (non‐tracking, non‐sequencing) operation of
IR3895, when Enable is used as a logic input. In this
operating mode Vref is left floating. Figure 5b shows the
recommended startup sequence for sequenced operation
of IR3895 with Enable used as logic input. For this mode
of operation, Vref is left floating. Figure 5c shows the
recommended startup sequence for tracking operation of
IR3895 with Enable used as logic input. For this mode of
operation, Vref should be connected to Gnd.
PRE‐BIAS STARTUP
IR3895 is able to start up into pre‐charged output, which
prevents oscillation and disturbances of the output
voltage.
The output starts in asynchronous fashion and keeps the
synchronous MOSFET (Sync FET) off until the first gate
signal for control MOSFET (Ctrl FET) is generated. Figure 6a
shows a typical Pre‐Bias condition at start up. The sync FET
always starts with a narrow pulse width (12.5% of a
switching period) and gradually increases its duty cycle
with a step of 12.5% until it reaches the steady state value.
The number of these startup pulses for each step is 16 and
it’s internally programmed. Figure 6b shows the series of
16x8 startup pulses.
HDRv
LDRv
Pre-Bias
Voltage
[V]
16
12.5%
Figure 6b: Pre‐Bias startup pulses
Figure 6a: Pre‐Bias startup
...
...
25%
...
...
16
...
...
...
...
87.5%
[Time]
IR3895
Vo
...
PD‐97746
...
End of
PB