IR3502MPBF International Rectifier, IR3502MPBF Datasheet - Page 25

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IR3502MPBF

Manufacturer Part Number
IR3502MPBF
Description
Complete VR11.0 or VR11.1 power solution.
Manufacturer
International Rectifier
Datasheet

Specifications of IR3502MPBF

Package
32-Lead MLPQ
Circuit
X-Phase Control IC
Switch Freq (khz)
250kHz to 1.5MHz
Pbf
PbF Option Available
Phase Number Determination
After a daisy chain pulse is started, the IR3502 checks the timing of the input pulse at PHSIN pin to determine the
phase number. This information is used to have symmetrical phase delay between phase switching without the
need of any external component.
Single Phase Operation
In an architecture where only a single phase is needed the switching frequency is determined by the clock
frequency.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at
least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The
crossover frequency of current share loop
Fault Operation Table
The Fault Table below describes the different faults that can occur and how IR3500A would react to protect the
supply and the load from possible damage. The fault types that can occur are listed in row 1. Row 2 has the method
that a fault is cleared. The first 5 faults are latched in the UV fault latch and the VCCL power has to be recycled by
switching off the input and switching it back on for the converter to work again. The rest of the faults (except for
UVLO Vout) are latched in the SS fault latch and does not need to recycle the VCCL power in order to resume
normal operation once the fault condition clears. Most of the faults disable the error amplifier (EA) and discharge the
soft start capacitor. All the faults flag VRRDY. VRRDY returns back to high when the faults are cleared. The delay
row shows reaction time after detecting a fault condition. Delays are provided to minimize the possibility of nuisance
faults.
ROSC/OVP
Error Amp
& IIN drive
Discharge
OV clears
high until
Disabled
Clearing
SS/DEL
Method
VRRDY
Delay?
Flags
Fault
Page 25 of 39
Open
Daisy
32 Clock
Pulses
PHSOUT
Control
Pulses
Open
Loop
No
8
Recycle VCCL
Sense
Open
Line
No
is approximately 8 kHz.
Voltage
Over
Yes
No
1.3us
Blank
Time
VID
Fault Type
Disable
250 ns
Blank
Time
Yes
Yes
Yes
Resume Normal Operation when Condition Clears
VCCL
UVLO
No
Programmed by
Pulses. Count
ROSC value
OC Before
PHSOUT
Start-up
No
July 28, 2009
SS/DEL Discharge
IR3502
Threshold
OC After
Start-up

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