TMPM382FWFG Toshiba, TMPM382FWFG Datasheet - Page 62

• Manufacturer Part Number: TMPM382FWFG
• Manufacturer: Toshiba

Specifications of TMPM382FWFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 12K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

7.1.2.3 Executing an ISR
7.1.2.4 Exception exit
the user.
occur again upon return to normal program execution.
the currently executing ISR and services the newly detected exception.
An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by
When returning from an ISR, the CPU takes one of the following actions:
If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons
(1) Execution after returning from an ISR
An ISR may need to include code for clearing the interrupt request so that the same interrupt will not
For details about interrupt handling, see “7.5 Interrupt”.
higher priority than all stacked exceptions, the CPU returns to the ISR of the pending exception.
one ISR and entering another. This is called “tail-chaining”.
than the highest priority pending exception, the CPU returns to the last stacked ISR.
If a pending exception exists and there are no stacked exceptions or the pending exception has
In this case, the CPU skips the pop of eight registers and push of eight registers when exiting
If there are no pending exceptions or if the highest priority stacked exception is higher priority
If there are no pending or stacked exceptions, the CPU returns to the previous program.
Tail-chaining
Returning to the last stacked ISR
Returning to the previous program
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