TMPM380FYDFG Toshiba, TMPM380FYDFG Datasheet - Page 551

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TMPM380FYDFG

Manufacturer Part Number
TMPM380FYDFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM380FYDFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
16K
Number Of Pins
100
Package
QFP(14×20)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
2
I2c/sio (ch)
2
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
18
16-bit Timer / Counter
8
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
22 DMA Controller (DMAC)
TMPM380/M382
22.4.13 DMACC0SrcAddr (DMAC Channel0 Source Address Register)
Address = (0x4008_0000) + 0x0100
Bit
Reset
Bit
Type
Description
Symbol
Value
[31:0]
SrcAddr
R/W
0x00000000
Sets a DMA transfer source address
[Explanation]
m. <SrcAddr>
Because enabling channels updates the data written in the registers, set DMACCxSrcAddr
before enabling the channels.
When the DMA is operating, the value in the DMACCxSrcAddr register sequentially changes, so
the read values are not fixed.
Do not update DMACC0SrcAddr during transfer. To change the value, be sure to set the
DMACCxConfiguration register to disable the channel before change.
• DMACCxSrcAddr (DMAC Channel x Source Address Register) (x = 1)
Refer to the description on DMACC0SrcAddr because the structures and explanations on the
above registers are the same as DMACC0SrcAddr. Also, refer to Table22-4 SFR list for register
names and addresses.
TMPM380/M382 - 16 / 26 -

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