TB6572AFG*** Toshiba, TB6572AFG*** Datasheet - Page 11

• Manufacturer Part Number: TB6572AFG***
• Manufacturer: Toshiba

Specifications of TB6572AFG***

• Function: Controller
• Vopmax (vm*): 17V (30V)
• Io (lpeak): 20mA
• Sinusoidal Current Wave: yes
• Sensor-less: no
• Speed Feedback Loop: yes
• Package: QFP52
• Rohs Compatible†: yes

Fref
signal
FG signal
FG signal
7. External FET Gate Drive Output
8. Speed Control
DOUT
< Dout output >
comparator
Impedance must be reduced when FETs are driven. To control
impedance, source and sink outputs are configured as shown at
right. Resistors are incorporated to control source and sink outputs
of FETs, and each resistor value is shown below.
Incorporated resistors
•
•
•
•
•
•
•
*: The internal system clock is generated by the on-chip PLL from an external clock. The system clock frequency
Low (accelerate trigger)
Phase
Source for upper FET: RU1 = 1 kΩ (typ.)
Sink for upper FET: RU 2 = 100 Ω (typ.)
Source for lower FET: RL1 = 1 kΩ (typ.)
Sink for lower FET: RL2 = 100 Ω (typ.)
The TB6572AFG uses a speed discriminator and PLL to control speed.
The maximum F
The speed discriminator has two counter stages, each of which alternately counts a single period of the
FG signal. The resulting difference signal is output as two signals (accelerate and decelerate triggers).
The PLL counts the phase difference between the 1/2 FG signal and reference signal. The resulting
difference signal is output as two signals (accelerate and decelerate triggers). The phase difference is
assumed to be zero when the FG frequency is outside the lock range (±6% of the specified value).
FG frequency = speed control clock/speed discriminator
→ Speed control clock = FG frequency × speed discriminator
When the Fref input is open, the output is turned off.
Note that a sudden variation in rotation speed may cause a motor current to be regenerated into the
power supply, resulting in the rise of the motor voltage.
may saturate, depending on the external LPF and VCO constants. The speed discriminator compares the
reference frequency derived from the system clock against the FG frequency. If the system clock frequency
saturates, the system clock is not synchronized to the FG signal. (Instead, the system clock is synchronized
with the reference frequency.) At this time, the READY signal remains Low. The LPF and VCO constants
should be optimized.
1024 counts
2.25 V
FG amp
frequency
1/1024
divider
FG frequency = 200 to 4000 k, speed discriminator = 1024
Speed control clock = 0.2048 to 4.096 MHz
System clock = speed control clock × 4 = 0.8192 to 16.38 MHz
LPF
ref
discriminator
value should be no greater than four times the minimum F
1024 counts
Speed
1.0 V
1024
VCO
1/4
High (decelerate trigger)
PLL
Control
Gain
3.5 V
< Pout output >
PLL from an external clock
Pout
11
Dout
Fref signal
FG signal
Fref signal
FG signal
POUT
POUT
Sine wave system clock
－
+
Integral amp
Speed control circuitry
2.25 V
1.0 V
LA(U)
LA(L)
OUT-A
2.25 V
3.5 V
amplifier
Control
ref
RU2
RU1
RL1
RL2
value.
High
(decelerate trigger)
Low
(accelerate trigger)
TB6572AFG
Upper FET
Lower FET
2008-1-21
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