TC62D748AFG Toshiba, TC62D748AFG Datasheet - Page 5

• Manufacturer Part Number: TC62D748AFG
• Manufacturer: Toshiba

Specifications of TC62D748AFG

• Package: SSOP24
• # Outputs: 16
• Vout Max: 17V
• Io: 1.5 to 90mA
• Io Accuracy: ±1.5%
• Features Error Detection: -
• Features Gain Control: -
• Features Pwm Dimming: -
• Other Features & Functions: Available in small QSOP24 package (outside Japan)
• Rohs Compatible Product(s) (#): Available

Truth Table
Timing Diagram
Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to
Note2: “-“ is irrelevant to the truth table.
SCK
・The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit.
・Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT
・This product can use 3.3V and 5.0V power supply, but power supply and input (SCK/SIN/ SLAT / OE )
pin is set to “H” the latch circuit does not hold data. The data will instead pass onto output.
When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to
the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of
the data.
must use same voltage.
"L" the respective output will be OFF.
OUT15
OUT0
OUT1
SLAT
OUT
SOUT
SCK
OE
SIN
2
n = 0
SLAT
− *2
− *2
H
H
L
1
2
3
4
OE
H
L
L
L
L
5
6
7
Dn + 1
Dn + 2
Dn + 3
Dn + 3
8
SIN
Dn
9
5
10
11
12 13
OUT0 … OUT7 … OUT15 *1
TC62D748AFG/AFNAG/BFNAG
Dn + 2 … Dn − 5 … Dn − 13
Dn + 2 … Dn − 5 … Dn − 13
Dn … Dn − 7 … Dn − 15
14
15
No Change
OFF
2011-02-08
H
L
H
L
H
L
H
L
ON
OFF
ON
OFF
ON
OFF
ON
OFF
H
L
Dn − 15
Dn − 14
Dn − 13
Dn − 13
Dn − 13
SOUT