74LCX16245MTD Fairchild Semiconductor, 74LCX16245MTD Datasheet - Page 2

• Manufacturer Part Number: 74LCX16245MTD
• Description: IC TXRX BIRDIR 16BIT 5V 48-TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LCXr

Specifications of 74LCX16245MTD

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Logic Family: 74LCX
• Number Of Channels Per Chip: 16
• Input Level: LVTTL, TTL
• Output Level: LVCMOS
• Output Type: 3-State
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 5.2 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Function: Transceiver
• Input Bias Current (max): 20 uA
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Circuits: 2
• Polarity: Non-Inverting
• Logic Device Type: Transceiver, Non Inverting
• Supply Voltage Range: 2V To 3.6V
• Logic Case Style: TSSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Family Type: LCX
• Rohs Compliant: Yes
• Dc: 03+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Connection Diagrams
Logic Diagrams
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
2
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
L
X
Z
OE
T/R
A
B
NC
0
0
LOW Voltage Level
High Impedance
Pin Names
OE
HIGH Voltage Level
Immaterial
OE
–A
–B
G
A
B
C
D
E
F
H
H
J
n
H
L
L
L
L
n
2
15
15
1
Inputs
Inputs
B
B
B
B
B
B
B
B
B
T/R
1
10
12
14
15
0
2
4
6
8
T/R
H
X
L
H
L
X
2
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
1
B
NC
B
NC
B
B
B
B
B
Bus B
Bus A
HIGH Z State on A
2
11
13
1
3
5
7
9
Bus B
Bus A
HIGH Z State on A
8
8
GND
GND
GND
T/R
T/R
–B
–A
V
V
0
0
NC
NC
–B
–A
3
CC
CC
15
15
1
2
Description
7
7
Data to Bus A
Data to Bus B
Data to Bus A
Data to Bus B
Outputs
GND
GND
GND
OE
OE
Outputs
V
V
NC
NC
4
CC
CC
1
2
8
–A
0
–A
15
7
A
NC
A
NC
, B
A
A
A
A
A
, B
5
11
13
1
3
5
7
9
8
8
0
0
8
–A
–B
0
–A
–B
–B
–B
15
15
7
7
15
7
A
A
A
A
A
A
A
A
A
6
10
12
14
15
0
2
4
6
8