MAX9242 Maxim, MAX9242 Datasheet
MAX9242
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MAX9242 Summary of contents
Page 1
... The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVC- MOS/LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9242/ MAX9244/MAX9246/MAX9254 feature spread-spectrum capability, allowing the output data and clock frequency to spread over a specified range to reduce EMI. The sin- gle-ended data and clock outputs are programmable for a frequency spread of ± ...
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... C = 8pF, L Non-DC-balanced worst-case pattern, mode (SSG = low 3.0V CC CCO to 3.6V, Figure anced (MAX9242 en) 34MHz MAX9244, MAX9254 anced m ode ( en) 40MHz = 330Ω 150pF 2.0kΩ 330pF) D ...
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Deserializers with Programmable Spread Spectrum and DC Balance DC ELECTRICAL CHARACTERISTICS (continued LVDSV = PLLV = +3.0V to +3.6V low, differential input voltage | 0.05V to 1.2V, input common-mode voltage V ...
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Deserializers with Programmable Spread Spectrum and DC Balance DC ELECTRICAL CHARACTERISTICS (continued LVDSV = PLLV = +3.0V to +3.6V low, differential input voltage | 0.05V to 1.2V, input common-mode voltage V ...
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... V and Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested +25°C. A Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current must be less than ±10µA. ...
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Deserializers with Programmable Spread Spectrum and DC Balance FAIL-SAFE IN2 COMPARATOR RxIN_ + OR RxIN_ + OR RxCLKIN+ RxCLKIN 0. IN1 IN1 R R IN1 IN1 RxIN_ - OR RxIN_ - ...
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... RCOH RSRC 2.0V RxOUT_ 0.8V Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times RCIP + RxCLKIN_ RCCD RxCLKOUT 1.5V Figure 6b. Clock-IN to Clock-OUT Delay (MAX9242) PWRDWN 1.5V RxCLKIN_ RPDD RxOUT_ RxCLKOUT Figure 8. Power-Down Delay _______________________________________________________________________________________ Test Circuits/Timing Diagrams (continued) RxCLKIN_ 0.8V 0.8V RCOL RHRC 2.0V 0.8V Figure 6a. Clock-IN to Clock-OUT Delay (MAX9244/MAX9246/ ...
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Deserializers with Programmable Spread Spectrum and DC Balance SSG RxCLKIN_ RxCLKOUT RxOUT_ TIMING SHOWN FOR FALLING-EDGE STROBE (MAX9244/MAX9246/MAX9254) PWRDWN = HIGH Figure 9. Phase-Locked-Loop Set Time from SSG Change FREQUENCY SSM f (MAX) RxCLKOUT f RxCLKIN_ ...
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Deserializers with Programmable Spread Spectrum and DC Balance (V = PLLV = LVDSV = V = +3.3V CCO voltage V = 1.2V +25°C, MAX9244/MAX9254, unless otherwise noted WORST-CASE AND PRBS SUPPLY ...
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Deserializers with Programmable Spread Spectrum and DC Balance (V = PLLV = LVDSV = V = +3.3V CCO voltage V = 1.2V +25°C, MAX9244/MAX9254, unless otherwise noted RxCLKOUT POWER SPECTRUM vs. ...
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Deserializers with Programmable Spread Spectrum and DC Balance PIN NAME 1 RxOUT17 Channel 2 Single-Ended Outputs 2 RxOUT18 3, 25, 32, GND Ground 38 RxOUT19 Channel 2 Single-Ended Outputs 5 RxOUT20 Three-Level-Logic, Spread-Spectrum Generator Control Input. SSG ...
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... CHANNEL 1 7 SERIAL-TO-PARALLEL FIFO CHANNEL 2 7 SERIAL-TO-PARALLEL PARALLEL STROBES CLK CLK CLOCK IN OUT PLL1 FIFO CONTROL MAX9242 SPREAD- MAX9244 SPECTRUM MAX9246 PLL (SSPLL) MAX9254 SSG PWRDWN Pin Description (continued) Functional Diagram 7 RxOUT0–RxOUT6 7 RxOUT7–RxOUT13 7 RxOUT14–RxOUT20 RxCLKOUT ...
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... Two complementary bits are appended to each group of 7 parallel-input data bits to indicate to the MAX9242/ MAX9244/MAX9246/MAX9254 deserializer whether the data bits are inverted (see Figures 11 and 12). The deserializer restores the original state of the parallel data ...
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... The PLL control voltage does not saturate in response to high-frequency glitches that may occur during a hot swap. The PWRDWN input on the MAX9242/MAX9244/MAX9246/ MAX9254 does not need to be cycled when these devices FUNCTION are connected to an active serializer. ...
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Deserializers with Programmable Spread Spectrum and DC Balance ±4% OR ±2% SPREAD SSG RxCLKOUT RxOUT_ Figure 13. Output Waveforms when Spread Amount is Changed SSG NO SPREAD RxCLKOUT RxOUT_ Figure 14. Output Waveforms when Spread is Added ±4% OR ...
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Deserializers with Programmable Spread Spectrum and DC Balance INTERNAL PLL1 LOCK INTERNAL SSPLL LOCK RxCLKOUT RxOUT_ Figure 16. Output Waveforms when PLL1 Loses Lock and Locks Again INTERNAL SSPLL LOCK RxCLKOUT RxOUT_ TIMING SHOWN FOR STABLE CLOCK AND DATA ...
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... transition time ( 100 droop (% of signal amplitude) Jitter due to 2% droop and assumed 1ns transition time is: The transition time in a real system depends on the fre- quency response of the cable driven by the serializer. MAX9242/MAX9244/MAX9246/MAX9254 7 1:7 FIFO 7 1:7 FIFO RxOUT_ 7 1:7 FIFO PWRDWN ...
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... Equation 1 altered for four series capacitors (Figure 20 DSV The MAX9242/MAX9244/MAX9246/MAX9254 have fail- safe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the corresponding LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low when power is stable ...
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... A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended. Layout PC board traces for 100Ω differential characteristic imped- with high-frequency, ance. The trace dimensions depend on the type of MAX9242/MAX9244/MAX9246/MAX9254 7 1:( FIFO 7 1:( RxOUT_ ...
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... CCO Rising- or Falling-Edge Output Strobe The MAX9242 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLKOUT. The MAX9244/MAX9246/ MAX9254 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLKOUT ...
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... Human Body Model, IEC 61000-4-2 and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic sys- tems. All LVDS inputs on the MAX9242/MAX9244/ MAX9246/MAX9254 meet ISO 10605 ESD protection at ±30kV Air-Gap Discharge and ±6kV Contact Discharge and IEC 61000-4-2 ESD protection at ± ...
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... For the latest package outline information and land patterns, go PIN-PACKAGE to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package draw- 48 TSSOP ings may show a different suffix character, but the drawing per- 48 TSSOP tains to the package regardless of RoHS status ...
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... Added automotive qualified parts to Ordering Information table Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...