MAX9210 Maxim, MAX9210 Datasheet - Page 9

• Manufacturer Part Number: MAX9210
• Description: The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs
• Manufacturer: Maxim

Figure 8. Power-Down Delay
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
Figure 10. Deserializer Serial Input in DC-Balanced Mode
PWRDWN
RxCLK OUT
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
TxIN_ IS DATA FROM THE SERIALIZER.
RxCLK IN
RxOUT_
CYCLE N - 1
+
-
RxCLK IN
RxIN2
RxIN1
RxIN0
DCA2
DCA1
DCA0
CYCLE N - 1
+
-
TxIN15
RxCLK IN
RxIN2
RxIN1
RxIN0
TxIN8
TxIN1
DCB2
DCB1
DCB0
TxIN14
TxIN7
TxIN0
TxIN20
TxIN13
TxIN6
_______________________________________________________________________________________
TxIN20
TxIN13
TxIN6
TxIN19
TxIN12
TxIN5
TxIN19
TxIN12
TxIN5
TxIN18
TxIN11
TxIN4
0.8V
TxIN18
TxIN11
TxIN4
RPDD
TxIN17
TxIN10
TxIN3
CYCLE N
CYCLE N
TxIN17
TxIN10
TxIN3
TxIN16
TxIN9
TxIN2
TxIN16
TxIN9
TxIN2
TxIN15
HIGH-Z
TxIN8
TxIN1
Programmable DC-Balance
TxIN15
TxIN8
TxIN1
TxIN14
TxIN7
TxIN0
TxIN14
DCA2
DCA1
DCA0
TxIN7
TxIN0
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9210/
MAX9214/MAX9220/MAX9222 deserializers whether
the data bits are inverted (see Figures 9 and 10). The
deserializer restores the original state of the parallel
data. The LVDS clock signal alternates duty cycles of
4/9 and 5/9, which maintain DC balance.
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
DCB2
DCB1
DCB0
TxIN20
TxIN13
TxIN6
21-Bit Deserializers
TxIN20
TxIN13
TxIN6
TxIN19
TxIN12
TxIN5
TxIN19
TxIN12
TxIN5
TxIN18
TxIN11
TxIN4
CYCLE N + 1
TxIN18
TxIN11
TxIN4
TxIN17
TxIN10
TxIN3
CYCLE N + 1
TxIN17
TxIN10
AC-Coupling Benefits
TxIN3
TxIN16
TxIN9
TxIN2
TxIN16
TxIN9
TxIN2
TxIN15
TxIN8
TxIN1
TxIN15
TxIN8
TxIN1
TxIN14
TxIN7
TxIN0
TxIN14
TxIN7
TxIN0
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