MAX9208 Maxim, MAX9208 Datasheet
MAX9208
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MAX9208 Summary of contents
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... The MAX9206/MAX9208 operate from a single +3.3V supply and are specified for operation from -40°C to +85°C. The MAX9206/MAX9208 are available in 28-pin SSOP packages ...
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... Storage Temperature Range .............................-65°C to +150°C CC ESD Rating (Human Body Model, RI+, RI-) .........................±8kV Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260° 0.1V to 1.2V, common-mode voltage V ID CONDITIONS C = 15pF, L MAX9206 worst-case CC pattern, MAX9208 Figure 1 PWRDWN = low 0V AVCC DVCC I = -5mA OH OH ...
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... V ID CONDITIONS MAX9206 RFF MAX9208 MAX9206 MAX9208 RFTT MAX9206 RCP MAX9208 Figure 3 CLH Figure 3 CHL MAX9206, 45MHz t Figure 4 DD MAX9208, 60MHz Figure 5 ROS Figure 5 ROH RDC C = 5pF, Figure 6 HZR 5pF, Figure 6 LZR 5pF, Figure 6 ZHR 5pF, Figure 6 ...
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... CONDITIONS PLL locked to stable REFCLK; supply stable; static input; measured from DSR2 start of sync patterns at input to LOCK transition low; Figure 8 Figure 7 ZHLK MAX9206 t Figure 9 JT MAX9208 = +25°C and guaranteed by design and characterization over operating temper +3.3V 1.1V, AVCC DVCC CM MIN TYP MAX ...
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PIN NAME 1, 12, 13 AGND Analog Ground Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe 2 RCLK_R/F ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling ...
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Bus LVDS Deserializers IN2 V - 0.3V CC RI+ R IN1 R IN1 RI- Figure 2. Input Fail-Safe Circuit START SYMBOL N BIT RCLK ROUT_ Figure 4. Input-to-Output Delay RCLK RCLK_R/F = ...
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PWRDN REFCLK t RFCP RI t ZHLK LOCK HIGH-Z RCLK HIGH-Z ROUT_ HIGH-Z 2048 x t Figure 7. PLL Lock Time from PWRDN REFCLK t RFCP RI LOCK RCLK ROUT_ Figure 8. Deserializer PLL Lock Time from _______________________________________________________________________________________ 10-Bit Bus ...
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... Detailed Description The MAX9206/MAX9208 deserialize a BLVDS serializ- er's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial input, and digital circuits that deserialize and deframe the data. The MAX9206/MAX9208 have high- input jitter tolerance while receiving data at speeds from 160Mbps to 600Mbps ...
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... The sum of the zero-to-peak individual jitter sources must be less than or equal to the minimum value of t For example, at 40MHz, the MAX9205 serializer has 140ps (p-p) maximum deterministic output jitter. The zero-to-peak value is 140ps/2 = 70ps. If the intercon- Input Fail-Safe nect jitter is 100ps (p-p) with a symmetrical distribution, the zero-to-peak jitter is 50ps ...
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... Differential Traces and Termination Trace characteristics affect the performance of the MAX9206/MAX9208. Use controlled-impedance media. Avoid the use of unbalanced cables such as ribbon or ASIC MAX9205 MAX9207 ...
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... Deserializer initialized High High Deserializer initialized X = Don’t care. The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of double-terminated point-to-point and point-to-point broadcast are shown in Figures 10 and 11. Use 1% surface-mount termina- tion resistors. A point-to-point interface terminated at each end in the characteristic impedance of the cable or PCB traces is shown in Figure 10 ...
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... Updated Ordering Information, Absolute Maximum Ratings, and Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...