MAX9174 Maxim, MAX9174 Datasheet

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MAX9174

Manufacturer Part Number
MAX9174
Description
The MAX9174/MAX9175 are 670MHz, low-jitter, low-skew 1:2 splitters ideal for protection switching, loopback, and clock and signal distribution
Manufacturer
Maxim
Datasheet

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The MAX9174/MAX9175 are 670MHz, low-jitter, low-
skew 1:2 splitters ideal for protection switching, loop-
back, and clock and signal distribution. The devices
feature ultra-low 1.0ps
ensures reliable operation in high-speed links that are
highly sensitive to timing errors.
The MAX9174 has a fail-safe LVDS input and LVDS out-
puts. The MAX9175 has an anything differential input
(CML/LVDS/LVPECL) and LVDS outputs. The outputs
can be put into high impedance using the power-down
inputs. The MAX9174 features a fail-safe circuit that dri-
ves the outputs high when the input is open, undriven
and shorted, or undriven and terminated. The MAX9175
has a bias circuit that forces the outputs high when the
input is open. The power-down inputs are compatible
with standard LVTTL/LVCMOS logic. The power-down
inputs tolerate undershoot of -1V and overshoot of V
+ 1V. The MAX9174/MAX9175 are available in 10-pin
µMAX and 10-lead thin QFN with exposed pad pack-
ages, and operate from a single +3.3V supply over the
-40°C to +85°C temperature range.
19-2827; Rev 1; 4/04
Functional Diagram and Pin Configurations appear at end
of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Protection Switching
Loopback
Clock Distribution
670MHz LVDS-to-LVDS and Anything-to-LVDS
________________________________________________________________ Maxim Integrated Products
General Description
(RMS)
CLK1
CLK2
random jitter (max) that
Applications
MAX9174
MAX9174
CLOCK DISTRIBUTION
CC
*Future product—contact factory for availability.
**EP = Exposed paddle.
MAX9174EUB
MAX9174ETB*
MAX9175EUB
MAX9175ETB*
1.0ps
80ps
+3.3V Supply
LVDS Fail-Safe Inputs (MAX9174)
Anything Input (MAX9175) Accepts Differential
CML/LVDS/LVPECL
Power-Down Inputs Tolerate -1.0V and V
Low-Power CMOS Design
10-Lead µMAX and Thin QFN Packages
-40°C to +85°C Operating Temperature Range
Conform to ANSI TIA/EIA-644 LVDS Standard
IEC 61000-4-2 Level 4 ESD Rating
PART
(P-P)
(RMS)
MAX9176
MAX9176
Jitter (max) at 800Mbps Data Rate
Typical Application Circuit
Jitter (max) at 670MHz
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
TEMP RANGE
Ordering Information
CLK IN
CLK IN
ASIC
ASIC
1:2 Splitters
PIN-PACKAGE
10 µMAX
10 Thin QFN-EP**
10 µMAX
10 Thin QFN-EP**
Features
CC
+ 1.0V
1

Related parts for MAX9174

MAX9174 Summary of contents

Page 1

... The MAX9174 has a fail-safe LVDS input and LVDS out- puts. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs ...

Page 2

... CC PD_ 1. Figure Figure 2 OD Figure 1.5kΩ 100pF PD0, PD1) ...............................................2kV CC = 330Ω 150pF 0.05V to 1.2V, MAX9174 input common-mode / /2|), +1.25V +25°C.) (Notes MIN TYP MAX +50 -50 -20 + 3.6V IN -20 ...

Page 3

... ID OD PD0 = V , PD1 = PD0 = 0V, PD1 = PD0 = Vcc, PD1 = Vcc PD1, PD0 = 0V I CCPD C OUT_+ or OUT_- to GND (Note 4) O 1:2 Splitters | = 0.05V to 1.2V, MAX9174 input common-mode / /2|), +1.25V +25°C.) (Notes MIN TYP MAX 1 ...

Page 4

... SKPP1 conditions. Note 10 the magnitude of the difference of any differential propagation delays between devices operating over rated con- SKPP2 ditions. Note 11: Meets all AC specifications. 4 _______________________________________________________________________________________ = 5pF, differential input voltage | 0.15V to 1.2V, MAX9174 input common-mode volt +3.3V 0.2V CONDITIONS Figures 4, 5 PHL ...

Page 5

... LVDS-to-LVDS and Anything-to-LVDS ((MAX9174 +3.3V 0.15V SUPPLY CURRENT vs. TEMPERATURE 155MHz -40 - TEMPERATURE (°C) DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE 3 155MHz IN 2.9 2.8 2.7 2.6 t PHL 2.5 2.4 2.3 2.2 t PLH 2.1 2.0 -40 - TEMPERATURE (°C) SUPPLY CURRENT vs. DATA RATE 45 23 ...

Page 6

... LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters ((MAX9174 +3.3V 0.15V DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE 3 155MHz IN 2.9 2.8 2.7 2.6 t PHL 2.5 2.4 2.3 t PLH 2.2 2.1 2.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE 2.8 2.7 2.6 t PHL 2.5 2.4 t PLH 2.3 2.2 0.075 0.825 INPUT COMMON-MODE VOLTAGE (V) OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE 8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 0.075 ...

Page 7

... P-P ensures reliable operation in high-speed links that are highly sensitive to timing error. The MAX9174 has a fail-safe LVDS input and LVDS out- puts. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs ...

Page 8

... VCC - 0.3V, activating the fail-safe circuit and forcing the outputs high (Figure 1). Overshoot and Undershoot Voltage The MAX9174/MAX9175 are designed to protect the power-down inputs (PD0 and PD1) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above VCC or below GND 1V, an internal circuit limits input current to 1 ...

Page 9

... The IEC 61000-4-2 model specifies a 150pF capacitor that is discharged Board Layout into the device through a 330Ω resistor. The MAX9174/ MAX9175 differential inputs and outputs are rated for IEC 61000-4-2 level 4 (±8kV Contact Discharge and ±15kV Air-Gap Discharge). The Human Body Model (HBM, Figure 10) specifies a 100pF capacitor that is discharged into the device through a 1.5kΩ ...

Page 10

LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters IN- IN+ OUT_- OUT_ (( OUT_ OUT_- (OUT_+) - (OUT_-) Figure 5. Transition Time and Propagation Delay Timing IN+ IN- OUT0+ OUT0- OUT1+ OUT1- Figure 6. Output-to-Output Skew ...

Page 11

... OUT_+ WHEN V = -50mV ID OUT_- WHEN V = +50mV ID Figure 7. Power-Up/Down Delay Waveform 1.25V IN+ 1.20V 1.25V IN- 1.20V PULSE GENERATOR 50Ω Figure 8. Power-Up/Down Delay Test Circuit ______________________________________________________________________________________ t PD 50% 50 MAX9174 MAX9175 1:2 Splitters -1. 50% 1.25V 1.25V 50 ...

Page 12

... OUT0- EXPOSED PAD IN- THIN QFN PD1 PD0 TRANSISTOR COUNT: 693 PROCESS: CMOS 1MΩ 1.5kΩ DISCHARGE RESISTANCE DEVICE C s STORAGE UNDER 100pF CAPACITOR TEST Functional Diagram OUT1+ MAX9174 MAX9175 LVDS DRIVER 1 OUT1- DIFFERENTIAL RECEIVER OUT0+ LVDS DRIVER 0 OUT0- Chip Information ...

Page 13

... LVDS-to-LVDS and Anything-to-LVDS (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages ÿ 0.50±0.1 0.6±0.1 1 0.6±0.1 TOP VIEW FRONT VIEW ______________________________________________________________________________________ ...

Page 14

... T1033-1 10 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...

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