MAX4802A Maxim, MAX4802A Datasheet - Page 10

• Manufacturer Part Number: MAX4802A
• Description: The MAX4800A/MAX4802A provide high-voltage switching on eight channels for ultrasonic imaging and printer applications
• Manufacturer: Maxim

Low-Charge-Injection, 8-Channel, High-Voltage
Analog Switches with 20MHz Serial Interface
Figure 2. Latch-Enable Interface Timing
The V
required to be symmetrical, but the voltage difference
V
The MAX4802A features integrated 35kΩ bleed resis-
tors to discharge capacitive loads such as piezoelec-
tric transducers. Each analog-switch terminal is
connected to RGND with a bleed resistor.
The devices are controlled by a serial interface with an
8-bit serial shift register and transparent latch. Each of
the eight data bits controls a single analog switch (see
Table 1). Data on DIN is clocked with the most signifi-
cant bit (MSB) first into the shift register on the rising
edge of CLK. Data is clocked out of the shift register
onto DOUT on the rising edge of CLK. DOUT reflects
the status of DIN, delayed by eight clock cycles (see
Figures 1 and 2).
10
PP
- V
______________________________________________________________________________________
DOUT
PP
NN
CLK
LE
DIN
and V
must not exceed 200V.
NN
high-voltage supplies are not
Bleed Resistors (MAX4802A)
D7
D7
MSB
Serial Interface
D6
D6
DATA FROM PREVIOUS DATA BYTE POWER-UP DEFAULT: D7–D0 = 0
D5
D5
D4
D4
Drive LE logic-low to change the contents of the latch
and update the state of the high-voltage switches
(Figure 2). Drive LE logic-high to freeze the contents of
the latch and prevent changes to the switch states. To
reduce noise due to clock feedthrough, drive LE logic-
high while data is clocked into the shift register. After
the data shift register is loaded with valid data, pulse
LE logic-low to load the contents of the shift register
into the latch.
The devices feature a latch clear input. Drive CLR
logic-high to reset the contents of the latch to zero and
open all switches. CLR does not affect the contents of
the data shift register. Pulse LE logic-low to reload the
contents of the shift register into the latch.
The devices feature a power-on reset circuit to ensure
all switches are open at power-on. The internal 8-bit ser-
ial shift register and latch are set to zero on power-up.
D3
D3
D2
D2
D1
D1
LSB
D0
D0
Latch Clear (CLR)
Latch Enable ( LE )
Power-On Reset
D7