MAX4742 Maxim, MAX4742 Datasheet - Page 7

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MAX4742

Manufacturer Part Number
MAX4742
Description
The MAX4741/MAX4742/MAX4743 are low on-resistance, low-voltage, dual single-pole/single-throw (SPST) analog switches that operate from a single +1
Manufacturer
Maxim
Datasheet

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The MAX4741/MAX4742/MAX4743 are low 0.8
(at V+ = +3V) on-resistance, low-voltage, dual analog
switches that operate from a +1.6V to +3.6V single sup-
ply. CMOS switch construction allows switching analog
signals that are within the supply voltage range (GND
to V+).
When powered from a +3V supply, the 0.8
allows high continuous currents to be switched in a
variety of applications.
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
Always sequence V+ on first, followed by NO_, NC_, or
COM_.
Although it is not required, power-supply bypassing
improves noise margin and prevents switching noise
propagation from the V+ supply to other components.
A 0.1µF capacitor, connected from V+ to GND, is ade-
quate for most applications.
The MAX4741/MAX4742/MAX4743 logic inputs can be
driven up to +3.6V regardless of the supply voltage.
For example, with a +1.8V supply, IN_ may be driven
low to GND and high to +3.6V. Driving IN_ rail-to-rail
minimizes power consumption.
µMAX/µDFN
1
2
3
4
5
6
7
8
MAX4741
0.8 , Low-Voltage, Single-Supply Dual SPST
SOT23-8
Applications Information
_______________________________________________________________________________________
8
7
6
5
3
4
1
2
Detailed Description
µMAX
1
2
3
4
5
6
7
8
MAX4742
PIN
SOT23-8
Logic Inputs
8
7
6
5
3
4
1
2
max R
µMAX
1
2
3
4
5
6
7
8
max
MAX4743
ON
SOT23-8
Analog signals that range over the entire supply voltage
(V+ to GND) can be passed with very little change in on-
resistance (see Typical Operating Characteristics). The
switches are bidirectional, so the NO_, NC_, and COM_
pins can be used as either inputs or outputs.
High-speed switches require proper layout and design
procedures for optimum performance. Reduce stray
inductance and capacitance by keeping traces short
and wide. Ensure that bypass capacitors are as close
to the device as possible. Use large ground planes
where possible.
8
7
6
5
3
4
1
2
NAME
COM1
COM2
GND
NO1
NC1
NO2
NC2
IN2
IN1
V+
Analog Switches
Analog Switch 1 Normally Open
Analog Switch 1 Normally Closed
Analog Switch 1 Common
Logic Control Input Switch 2
Ground
Analog Switch 2 Normally Open
Analog Switch 2 Normally Closed
Analog Switch 2 Common
Logic Control Input Switch 1
Positive Supply Voltage
Analog Signal Levels
Pin Description
FUNCTION
Layout
7

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