DS1842 Maxim, DS1842 Datasheet - Page 2

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DS1842

Manufacturer Part Number
DS1842
Description
The DS1842 integrates the discrete high-voltage components necessary for avalanche photodiode (APD) bias and monitor applications
Manufacturer
Maxim
Datasheet

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76V, APD, Bias Output Stage with
Current Monitoring
ABSOLUTE MAXIMUM RATINGS
Voltage Range on GATE and CLAMP
Voltage Range on MIRIN, MIROUT,
Voltage Range on LX Relative to GND...................-0.3V to +85V
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
ELECTRICAL CHARACTERISTICS
(T
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
Note 2: Rising MIROUT transition from 10µA to 1mA; V
Note 3: Guaranteed by design; not production tested.
2
Switching Frequency
FET Capacitance
FET Gate Resistance
FET On-Resistance
GATE Voltage
Switching Current
LX Voltage
LX Leakage
CLAMP Voltage
CLAMP Threshold
Maximum MIROUT Current
MIR1 to MIROUT Ratio
MIR2 to MIROUT Ratio
MIR1, MIR2 Rise Time (20%/80%)
Shutdown Temperature
Leakage on GATE and CLAMP
Relative to GND...................................................-0.3V to +12V
MIR1, and MIR2 Relative to GND........................-0.3V to +80V
Junction-to-Ambient Thermal Resistance (θ
Junction-to-Case Thermal Resistance (θ
A
= -40°C to +85°C, unless otherwise noted.)
_______________________________________________________________________________________
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PARAMETER
SYMBOL
I
V
R
MIROUT
C
T
K
K
JC
I
CLAMP
IL(LX)
V
DSON
V
C
SHDN
f
GATE
V
R
MIR1
MIR2
t
I
I
SW
RC
CLT
LX
) ...................8°C/W
GS
LX
IL
LX
G
JA
) ............41°C/W
V
f
V
V
Duty cycle = 10%, f
V
CLAMP = low
CLAMP = high
I
I
15V < V
I
I
15V < V
(Note 2)
(Note 3)
SW
MIROUT
MIROUT
MIROUT
MIROUT
GS
GS
GS
GATE
MIRIN
= 1MHz
= 0V, V
= 3V, I
= 10V, I
= 0V, V
MIRIN
MIRIN
= 1mA
= 1μA
= 1mA
= 1μA
= 40V, 2.5kΩ load.
D
DS
D
= 170mA
CONDITIONS
< 76V
< 76V
LX
= 170mA
= 25V
= 76V
Continuous Power Dissipation (T
Operating Junction Temperature Range ...........-40°C to +150°C
Storage Temperature Range .............................-55°C to +135°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
TDFN (derate 24.4mW/°C above +70°C).................1951.2mW
SW
= 100kHz
0.095
0.094
0.190
0.188
1.75
MIN
-1
-1
0
0
0
2
A
= +70°C)
0.100
0.100
0.200
0.200
+150
TYP
4.6
3.7
2.6
40
90
22
30
4
0.105
0.106
0.210
0.212
MAX
680
1.2
+1
+1
10
11
80
11
10
8
7
4
UNITS
MHz
A/A
A/A
mA
mA
μA
μA
μA
pF
ns
°C
V
V
V
V

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