MAX1512ETA+T Maxim Integrated Products, MAX1512ETA+T Datasheet - Page 11

• Manufacturer Part Number: MAX1512ETA+T
• Description: IC CALIBRATOR TFT VCOM 8-TDFN
• Manufacturer: Maxim Integrated Products
• Type: TFT VCOM Calibratorr

Specifications of MAX1512ETA+T

• Applications: LCD TV/Monitor
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8. Conceptual Programming Circuit
The VCOM adjustment and the EEPROM programming
must be performed with an external programming cir-
cuit. Refer to the MAX1512 evaluation kit for a complete
programming circuit solution.
Use a circuit similar to the conceptual diagram shown in
Figure 8 to drive CTL. The accuracy of the programming
voltage (V
tion. The use of a comparator is recommended to verify
the correct programming voltage has been reached. A
complete design example of a CTL programming circuit
is presented in the MAX1512 evaluation kit data sheet.
Often, CTL and CE are exposed at the panel connector
and are therefore subject to electrostatic discharge
(ESD). Resistor-capacitor (RC) filters can be employed
at these inputs to improve their ESD performance
(Figure 9).
Figure 9. Improved EOS/Surge Performance
PROGRAMMING,
FLOATING AFTER
FLOATING AFTER
PROGRAMMING
EEPROM-Programmable TFT VCOM Calibrator
PROGRAMING
V
DD
DURING
PP
Electrostatic Discharge (CTL, CE)
) is critical for proper MAX1512 data reten-
Applications Information
INTERFACE
USER
______________________________________________________________________________________
10kΩ
1kΩ
100kΩ
R
CE
0.1µF
0.1µF
µC
V
PP
VERIFY
CE
CTL
MAX1512
GND
V
0 TO 2.5V
DD
DAC
REF
If the CE panel connector is to be left floating after pro-
gramming, be sure to include a resistor to ground (R
to ensure a valid logic-low on CE. The time constant for
a CE filter is not critical but the driving resistor must
have a much lower resistance than RCE to properly
drive CE.
If a filter is used at the CTL panel connector, its RC time-
constant should be short enough to avoid interfering with
CTL pulses or EEPROM programming timing. A time
constant less than 200µs does not interfere with EEP-
ROM programming. To avoid interfering with CTL puls-
es, make the time constant small compared to the CTL
pulsewidth used.
The CTL pin is internally biased to V
sitive to leakage currents above 0.1µA. When CTL is
not driven, avoid leakage currents around the CTL pin.
Otherwise, reinforce the V
nal resistive voltage-divider.
Use the following guidelines for good layout:
•
•
•
Refer to the MAX1512 evaluation kit for an example of
proper board layout.
Place the VCOM buffer and the R1/R2 voltage-
divider close to the OUT pin (Figure 1). Keep the
VCOM buffer and the R1/R2 voltage-divider close
to each other.
Place R
In noisy environments, bypass capacitors may be
desired on V
capacitors close to the IC with short connections to
the pins.
0 TO 15.5V
SET
close to SET.
DD
and/or V
CTL
DD
Leakage Current (CTL)
MAX1512
/ 2 set point with an exter-
AVDD
Layout Information
DD
. Keep any bypass
/ 2, but it is sen-
CE
11
)