LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 4

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Pin Descriptions
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
–
1
2
3
4
5
6
7
8
9
Fout4 (OSCin)
NO_ALIGN
NO_LOCK
Pin Name
CLKout4–
CLKout4+
CLKout3+
CLKout3–
CLKout2+
CLKout2–
NO_REF
ADDR
Cbyp3
Cbyp4
Cbyp2
Fout3
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
DAP
SDA
SCL
INIT
Hin
Vin
Fin
I/O
I/O
I/O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
I
I
I
I
I
I
Signal Level
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
LVDS
LVDS
LVDS
GND
GND
GND
I
I
2
2
C
C
4
Die Attach Pad (Connect to ground on PCB)
3.3V supply for PLL1
3.3V supply for logic I/O
Horizontal sync reference signal
Auto polarity correction for HVF will be based off Hin polarity.
Recognized clock inputs can be applied to Hin.
Vertical sync reference signal
Field sync (odd/even) reference signal
Reset signal for audio-video phase alignment (rising edge
triggered)
I
Pin settings:
– Tie low: 65h (7-bit slave address in hex)
– Float: 66h
– Tie high: 67h
I
I
3.3V supply for logic I/O
Loss of lock status flag for PLLs 1-4 (active high)
Loss of alignment status flag for OUTs 1–4 (active high)
Loss of reference status flag (active high)
Audio clock from PLL4 (fundamental rate is 98.304 MHz).
The output is 24.576 MHz by default and is selectable via the
host.
3.3V supply for CLKout4
Audio frame timing signal for OUT4 (active low.) Timing
Generator fixed to PLL4 clock. The output is the audio-video-
frame (AVF) pulse by default and is programmable via the host.
Optional OSCin function can be used to apply a 27 MHz external
clock for PLL4 to generate an audio clock independent of the
video input reference; this function must be enabled via the host.
Ground
3.3V supply for PLL3 and PLL4
3.3V supply for CLKout3
Ground
Video frame timing signal for OUT3 (active low). Timing generator
assignable to PLL1, PLL2, or PLL3. OUT3 format is selectable
via the host.
Video clock from PLL1, PLL2, or PLL3 depending on output
crosspoint mode. The output is 148.35 MHz by default and is
selectable via the host.
Bias bypass for on-chip LDO for PLL3
Connect to 1.0 uF and 0.1 uF bypass capacitors.
Bias bypass for on-chip LDO for PLL4
Connect to 1.0 uF and 0.1 uF bypass capacitors.
Bias bypass for on-chip LDO for PLL2
Connect to 1.0 uF and 0.1 uF bypass capacitors.
Video clock from PLL1, PLL2, or PLL3 depending on output
crosspoint mode. The output is 148.5 MHz by default and is
selectable via the host.
2
2
2
C address select
C Data signal
C Clock signal
Pin Description