EL1881CSZ Intersil, EL1881CSZ Datasheet
EL1881CSZ
Specifications of EL1881CSZ
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EL1881CSZ Summary of contents
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... SO (Pb-free) (See Note) EL1881CSZ-T7 8-Pin SO (Pb-free) (See Note) EL1881CSZ-T13 8-Pin SO (Pb-free) (See Note) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C ...
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Absolute Maximum Ratings ( Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Descriptions PIN NUMBER PIN NAME 1 Composite Sync Out 2 Composite Video In 3 Vertical Sync Out 4 GND 5 Burst/Back Porch Output 6 RSET (Note 1) 7 Odd/Even Output 8 VDD 5V NOTE must be a ...
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Typical Performance Curves Supply Current vs Temperature R =681kΩ SET 1.65 5.5V 1.6 1.55 4.5V 1.5 1.45 1.4 1.35 -50 -25 0 Temperature (°C) Clamp Discharge Current vs Temperature R =681kΩ SET 11.4 11.3 5.5V 11.2 11.1 4.5V 11 10.9 ...
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Typical Performance Curves Burst/Back Porch Width =5V, T =25° 200 400 R Vertical Sync Width =5V, T =25° 350 300 250 200 150 100 ...
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Typical Performance Curves Burst/Back Porch Delay vs Temperature R =681kΩ SET 250 5.5V 200 150 4.5V 100 50 0 -50 -25 0 Temperature (°C) Vertical Sync Default Delay Time vs Temperature R =681kΩ SET 64.5 63.5 5.5V 62.5 5V 61.5 ...
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Timing Diagrams NOTES: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even ...
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Expanded Timing Diagrams 8 EL1881C FIGURE 2. STANDARD VERTICAL TIMING FIGURE 3. NON-STANDARD VERTICAL TIMING FN7018.1 ...
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Applications Information Video In A simplified block diagram is shown following page coupled video signal is input to Video In pin 2 via nominally 0.1µF. Clamp charge current will prevent the signal on pin 2 from going any ...
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Vertical Sync A low-going Vertical Sync pulse is output during the start of the vertical cycle of the incoming video signal. The vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, followed by ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...