MAX7302 Maxim, MAX7302 Datasheet - Page 13

• Manufacturer Part Number: MAX7302
• Description: The MAX7302 I²C-/SMBus™-compatible, serial-interfaced peripheral features 9 level-translating I/Os, and operates from a 1
• Manufacturer: Maxim

When debouncing is enabled for a port input, transition
detection applies to the stored debounced input signal
value, rather than to the instantaneous value at the
input. This process allows for useful transition detection
of noisy signals, such as keyswitch inputs, without
causing spurious interrupts.
Any transition on ports configured as inputs automatically
set the D1 bit of that port’s I/O registers high. Any input can
be selected to assert an interrupt output indicating a transi-
tion has occurred at the input port(s). The MAX7302 sam-
ples the port input (internally latched into a snapshot
register) during a read access to its port P_ I/O register.
The MAX7302 continuously compares the snapshot with
the port’s input condition. If the device detects a change
for any port input, an internal transition flag sets for that
port. Read register 0x26 to clear the interrupt, then read all
the port I/O registers (0x01 to 0x09) by initiating a burst
read to clear the MAX7302’s internal transition flag. Note
that when debouncing is enabled for a port input, transition
detection applies to the stored debounced input signal
value, rather than to the instantaneous value at the input.
Transition bits D4 and D3 must be set to 0 to detect the
next rising or falling edge on the input port P_.
The MAX7302 allows the user to select the input port(s)
that cause an interrupt on the INT output. Set INT for
each port by using the INTenable bit (bit D5) in each
port P_ register. The appropriate port’s transition flag
always sets when an input changes, regardless of the
port’s INTenable bit settings. The INTenable bits allow
processor interrupt only on critical events, while the
inputs and the transition flags can be polled periodical-
ly to detect less critical events.
When debounce is disabled, signal transtions between
the 9th and 11th falling edges of clock will not be regis-
tered since the transition is detected and cleared at the
same read cycle.
Ports configured as outputs do not feature transition
detection, and therefore, cannot cause an interrupt.
The exception to this rule is the CLA outputs.
Table 8. Port Lock Registers
ADDRESS
Level-Translating GPIO and LED Driver with CLA
CODE
0x72
0x73
Port Input Transition Detection and Interrupt
Port
D7
P5
—
______________________________________________________________________________________
Port
D6
P4
—
Port
D5
P3
—
SMBus/I
Port
D4
P2
—
REGISTER DATA
The INT output never reasserts during a read sequence
because this process could cause a recursive reentry
into the interrupt service routine. Instead, if a data
change occurs during the read that would normally set
the INT output, the interrupt assertion is delayed until
the STOP condition. If the changed input data is read
before the STOP condition, a new interrupt is not
required and not asserted. The INT bit and INT output
(if selected) have the same value at all times.
The Transition bit in device configuration register 0x26 is
a NOR of all the port I/O registers’ individual Transition
bits. A port I/O register’s Transition bit sets when that
port is set as an input, and the input changes from the
port’s I/O registers last read through the serial interface.
A port’s individual Transition bit clears by reading that
port’s I/O register. The Transition flag of configuration
register 0x26 is only cleared after reading all port I/O
registers on which a transition has occurred.
The active-low RST input operates as a hardware reset
which voids any on-going I
MAX7302. This feature allows the MAX7302 supply cur-
rent to be minimized in power critical applications by
effectively disconnecting the MAX7302 from the bus.
RST also operates as a chip enable, allowing multiple
devices to use the same I
MAX7302 has its RST input high at any time. RST can
be configured to restore all port registers to the power-
up settings by setting bit D0 of device configuration reg-
ister 0x26 (Table 1). RST can also be configured to reset
the internal timing counters used for PWM and blink by
setting bit D1 of device configuration register 0x26.
When RST is low, the MAX7302 is forced into the I
STOP condition. The reset action does not clear the
interrupt output INT. The RST input is referenced to V
and is overvoltage tolerant up to the supply voltage, V
2
Port
Port
D3
P1
P9
C Interfaced 9-Port,
Port
D2
P8
—
2
2
C slave address if only one
C transaction involving the
Configuration
register 0x27
Port
D1
P7
Transition Flag
RST Input
Port
D0
P6
0
LA
2
DD
13
C
.