DS4550 Maxim, DS4550 Datasheet - Page 12

• Manufacturer Part Number: DS4550
• Description: The DS4550 is a 9-bit, nonvolatile (NV) I/O expander with 64 bytes of NV user memory controlled by either an I²C-compatible serial interface or an IEEE® 1149
• Manufacturer: Maxim

CLAMP. All digital outputs of the device output data
from the Boundary Scan parallel output while connect-
ing the Bypass test data register between TDI and
TDO. The outputs do not change during the CLAMP
instruction.
HIGHZ. All digital outputs of the device are placed in a
high-impedance state. The Bypass test data register is
connected between TDI and TDO.
IDCODE. When the IDCODE instruction is latched into
the parallel Instruction register, the Identification test
data register is selected. The device identification code
is loaded into the Identification test data register on the
rising edge of TCK following entry into the Capture-DR
state. Shift-DR can be used to shift the identification
code out serially through TDO. During Test-Logic-
Reset, the identification code is forced into the
Instruction register. The ID code always has a 1 in the
LSB position. The next 11 bits identify the manufactur-
er’s JEDEC number and number of continuation bytes
followed by 16 bits for the device and 4 bits for the ver-
sion. See the diagram below.
ADDRESS. This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the DS4550. When the ADDRESS instruction is
latched into the Instruction register, TDI connects to
TDO through the 8-bit Memory Address test data regis-
ter during the Shift-DR state.
READ. This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the DS4550. When the READ instruction is latched
into the Instruction register, TDI connects to TDO
through the 8-bit Memory Read test data register dur-
ing the Shift-DR state.
WRITE. This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the DS4550. When the WRITE instruction is latched
into the Instruction register, TDI connects to TDO
through the 8-bit Memory Write test data register during
the Shift-DR state. When EEPROM writes occur using
the JTAG interface, the DS4550 will write the whole EEP-
ROM memory page (8 bytes) even though only a single
byte is modified. The unmodified bytes of the page are
transparently rewritten to their current values. The
I
Expander Plus Memory
32-Bit ID Code
12
MSB
2
C and JTAG Nonvolatile 9-Bit I/O
Version (4 Bits)
____________________________________________________________________
0000
0001000000000000
Device ID (16 Bits)
Manufacturer ID (11 Bits)
DS4550’s EEPROM write cycles are specified in the
Nonvolatile Memory Characteristics table. The specifica-
tion shown is at the worst-case temperature. It is capa-
ble of handling many more writes at room temperature.
IEEE 1149.1 requires a minimum of two test data regis-
ters; the Bypass Register and the Boundary Scan
Register. The optional Identification test data register
has been included in the DS4550 design along with
three DS4550 specific registers (Address, Read, Write)
to support access to the EEPROM.
Bypass Register. This is a one-bit shift register used in
conjunction with the BYPASS, CLAMP, and HIGHZ instruc-
tions. It provides a short path between TDI and TDO.
Boundary Scan Register. This register contains both a
shift register path and a latched parallel output for all
control cells and digital I/O cells. It is 33 bits in length.
See
Identification Register. The Identification test data
register contains a 32-bit shift register and a 32-bit
latched parallel output. This register is selected during
the IDCODE instruction and when the TAP controller is
in the Test-Logic-Reset state.
Memory Address Register. This 8-bit register has a
latched parallel output that holds the memory address
location that is to be read from or written to. This regis-
ter is selected during the ADDRESS instruction.
Memory Read Register. This 8-bit load-only register
will latch the 8-bit value from the memory location indi-
cated by the address contained in the Address test
data register during the Capture-DR state. The data
can then be shifted out the TDO serial output by 8 ris-
ing edges of TCK during the Shift-DR state. See
4 for a detailed example.
Memory Write Register. This 8-bit output-only register
will write its 8-bit value to the memory location indicated
by the address contained in the Address test data reg-
ister during the Update-DR state. The data is shifted
into the Write test data register through the TDI input
with 8 rising edges of TCK during the Shift-DR state
immediately prior to the Update-DR state. See
for a detailed example.
00010100001
Table
3 for the cell bit locations and definitions.
Test Data Registers
Fixed Value (1 Bit)
1
Table
LSB
Table
5