DS4510 Maxim, DS4510 Datasheet
DS4510
Related parts for DS4510
DS4510 Summary of contents
Page 1
... Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and General Description The DS4510 is a CPU supervisor with integrated 64- byte EEPROM memory and four programmable, non- volatile (NV) I/O pins configured with an 2 industry-standard I C interface using either fast-mode (400kbps) or standard-mode (100kbps) communica- tion. The I/O pins can be used as general-purpose I to-parallel I/O expander with unlimited read/write capability ...
Page 2
... Storage Temperature Range .............................-55°C to +125°C Relative Soldering Temperature .......................................See IPC/JEDEC 3 CONDITIONS V (Notes (Note CONDITIONS DS4510U-5 DS4510U-10 CCTP DS4510U- 5.0V (Note 3) STBY 3mA sink current V OL 6mA sink current 4mA sink current OLIOX 10mA sink current (Note 4) OLRST R P ...
Page 3
CPU Supervisor with Nonvolatile Memory and CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See (V = 2.7V to 5.5V -40°C to +85°C PARAMETER SYMBOL RST Active Time Detect to RST V CC Fail to RST ...
Page 4
... Writes Note 1: All voltages referenced to ground. Note 2: The DS4510 does not obstruct the SDA and SCL lines if V inputs do not violate their min and max input voltage levels. Note 3: I STBY specified with V equal to 5.0V, and control port-logic pins are driven to ground or V ...
Page 5
CPU Supervisor with Nonvolatile Memory and (V = +5.0V +25°C, unless otherwise noted TRIP POINT vs. TEMPERATURE CC 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 -40 - ...
Page 6
... BIDIRECTIONAL NONVOLATILE I/O LATCHES PULLUP ENABLE (F0h) I/O CONTROL (F4h-F7h) X I/O STATUS (F8h) determines if the power-on reset level of the DS4510 is surpassed The trip point bit determines and the reset status bit is set if RST is is above V CCTP in its active state. Note: The RST pin is an open-drain output, therefore an external pullup resistor must be used to realize high logic levels ...
Page 7
... CPU Supervisor with Nonvolatile Memory and transistors. Read the I/O status register (F8h) to deter- mine the logic levels present at the I/O pins. Three types of memory are present in the DS4510 (EEPROM, SEEPROM, and SRAM). The main user memory is 64 bytes of EEPROM starting at address 00h. This memory is not SRAM shadowed, so all writes to these locations result in EEPROM write cycles regardless of the state of the SEE bit ...
Page 8
CPU Supervisor with Nonvolatile Memory and Programmable I/O REGISTER REGISTER LOCATION NAME Bit 7 (HEX) User 00-3F EE EEPROM Reserved 40-EF n/a Pullup F0 SEE Enable RST Delay F1 SEE User SEE F2 SEE User SEE F3 SEE I/O3 F4 ...
Page 9
... This register reflects the logic level of the I/O always read zero. This register contains 5 bits that read and control the behavior of the part as follows: Bit Function Reads zero when V is above the DS4510's power-on reset voltage. CC Reads one when V below CCTP Reads one when the RST pin is active ...
Page 10
... The DS4510 can write bytes (one page or row) with a single write transaction. This is internally con- trolled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent ...
Page 11
... It is possible to take advantage of that phenomenon by repeated addressing the DS4510, which allows the next page to be written as soon as the DS4510 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period elapse before attempting to write again to the W DS4510 ...
Page 12
... For the latest package outline information www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...