73S8024C Maxim, 73S8024C Datasheet - Page 13
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73S8024C
Manufacturer Part Number
73S8024C
Description
The 73S8024C is a single smart card interface IC, compliant to the electrical requirements of ISO 7816-3 and EMV 4
Manufacturer
Maxim
Datasheet
1.73S8024C.pdf
(22 pages)
DS_8024C_023
12 Typical Application Schematic
Rev. 1.3
NOTES:
1) VDD supply must be =2.7V to 3.6V DC.
2) Optional, can be left open
3) Required if external clock from uP is used.
4) Required if crystal is used.
5) Pin can not float. Must be driven or connected to GND
if power down function is not used.
6)Internal pull-up allows it to be left open if unused.
7) Rext1 and Rext2 are external resistors to ground and
Vdd to modify the VDDfault voltage. Can be left open
8) Keep L1 close to pin 5
Y1, C2 and C3 must be removed if external clock is used.
See NOTE 1
CLKDIV1_f rom_uC
CLKDIV2_f rom_uC
5V/3V_select_f rom_uC
PWRDN_f rom_uC
VDD
100nF
C4
See NOTE 5
VDD
C5
10uF
R2
20K
Figure 9: 73S8024C Typical Application Schematic
See note 8
L1
10uH
VDD
Card detection
switch is
normally
closed.
10
11
12
13
14
U5
1
2
3
4
5
6
7
8
9
See NOTE 6
73S8024C
CLKDIV1
CLKDIV2
5V3V_
GND
LIN
VDD
NC
PWRDN
PRESB
PRES
I/O
AUX2
AUX1
GND
Smart Card Connector
CMDVCC_
VDD_ADJ
XTALOUT
AUX2UC
AUX1UC
XTALIN
RSTIN
I/OUC
SO28
OFF_
GND
VDD
VCC
RST
CLK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK track should be routed
far from RST, I/O, C4 and
C8.
NDS & ISO7816=1uF, EMV=3.3uF
C1
Low ESR (<1 00mohms) C1
should be placed near the SC
connecter contact
See
note 7
R3
R1
Rext2
Rext1
See
NOTE 1
100nF
AUX2UC_to/f rom_uC
AUX1UC_to.f rom_uC
C6
IOUC_to/f rom_uC
VDD
See NOTE 2
73S8024C Data Sheet
External_clock_f rom uC
CRY STAL
Y 1
- OR -
See NOTE 4
OFF_interrupt_to_uC
RSTIN_f rom_uC
CMDVCC_f rom_uC
See NOTE 3
22pF
C2
22pF
C3
13