73S8010C Maxim, 73S8010C Datasheet - Page 8

• Manufacturer Part Number: 73S8010C
• Description: The 73S8010C is a single smart card interface IC, compliant to the electrical requirements of ISO 7816-3 and EMV 4
• Manufacturer: Maxim

ACK bit is sent to the master by the device. The master should send the STOP condition after receiving
the ACK bit.
2.2 Host Interface Status
Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04).
I
The I
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is the opcode bit (R/W). A ‘one’ indicates the master will read data from the status
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The device now starts
sending the 8-bit status register data to the control register during the DATA bits time. After the DATA
bits, the ‘one’ ACK bit is sent to the device by the master. The master should send the STOP condition
after receiving the ACK bit.
8
2
Name
PRES
PRESL
I/O
SUPL
PROT
MUTE
EARLY
ACTIVE
C-bus Read from the Status Register:
2
C-bus Read Command from the Status Register follows the format shown in
Bit
0
1
2
3
4
5
6
7
Description
Set when the card is present; reset when the card is not present.
Set when the PRES pin changes state (rising/falling edge); reset when the status
register is read. Generates an interrupt when set
Set when I/O is high; reset when I/O is low.
Set when a voltage fault is detected; reset when the status register is read.
Generates an interrupt when set.
Set when an over-current or over-heating fault has occurred during a card session;
reset when the status register is read. Generates an interrupt when set.
Set during ATR when the card has not answered during the ISO 7816-3 time
window (40000 card clock cycles); reset when the next session begins or this
register is read.
Set during ATR when the card has answered before 400 card clock cycles; reset
when the next session begins or this register is read.
Set when the card is active (V
Figure 2: I
Table 3: Host Status Register
2
C Bus Write Protocol
CC
is on); reset when the card is inactive.
Figure
3.
Rev. 1.5