MAXQ3183 Maxim, MAXQ3183 Datasheet - Page 41

• Manufacturer Part Number: MAXQ3183
• Description: The MAXQ3183 is a dedicated electricity measurement front-end that collects and calculates polyphase voltage, current, power, energy, and many other metering and power-quality parameters of a polyphase load
• Manufacturer: Maxim

This register specifies the threshold value for the vector sum (of three phase currents or three phase currents plus
the neutral current, configurable in the AUX_CFG register) as a fraction of the full-scale current. When the vector sum
(RMS) value exceeds this threshold value in one DSP cycle, the ISUMOVF flag in the IRQ_FLAG register is set. If the
IRQ_MASK.EISUM bit is set, the interrupt pin is driven active. The host must clear the interrupt flag. Full scale is rep-
resented by 0x10000. The maximum value allowed is 0xFFFF.
The X.FLAGS register contains condition flags that relate to the function of phase X (A/B/C) measurements. Once
set, these bits can be cleared only by the host.
Bit:
Name:
Reset:
Bit:
Name:
Reset:
Bit:
Name:
Reset:
BIT
7:6
5
4
3
2
1
0
DCHRF
DCHAF
NOZXF
NAME
OCF
OVF
UVF
Low-Power, Multifunction, Polyphase AFE
—
______________________________________________________________________________________
15
—
7
7
0
Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C)
Reserved.
Reactive Energy Direction Change. Set when the direction of reactive power flow changes (from
capacitive to inductive or from inductive to capacitive). If the DCHRM bit is set, this bit sets the DCHR
flag in the IRQ_FLAG register.
Real Energy Direction Change. Set when the direction of real power flow changes (from toward the load
to toward the line, or from toward the line to toward the load). If the DCHAM bit is set, this bit sets the
DCHA flag in the IRQ_FLAG register.
No-Zero Crossing. Set when the voltage waveform in phase X fails to exhibit a zero crossing during one
DSP cycle. If the NOZXM bit is set, this bit sets the NOZX flag in the IRQ_FLAG register.
Undervoltage. Set when the RMS voltage in phase X falls below the undervoltage threshold set in
UVLVL. If the UVM bit is set, this bit sets the UV flag in the IRQ_FLAG register.
Overvoltage. Set when the RMS voltage in phase X exceeds the overvoltage threshold set in OVLVL. If
the OVM bit is set, this bit sets the OV flag in the IRQ_FLAG register.
Overcurrent. Set when the RMS current in phase X exceeds the overcurrent threshold set in OCLVL. If
the OCM bit is set, this bit sets the OC flag in the IRQ_FLAG register.
with Harmonics and Tamper Detect
14
—
6
6
0
DCHRF
13
5
5
0
Vector Sum Threshold High Byte
Vector Sum Threshold Low Byte
Current Vector Sum Threshold (ISUMLVL) (0x054)
DCHAF
12
4
4
0
0xFF
0xFF
FUNCTION
NOZXF
11
3
3
0
Phase Status Registers
UVF
10
2
2
0
OVF
9
1
1
0
OCF
8
0
0
0
41