71M6531D Maxim, 71M6531D Datasheet
71M6531D
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71M6531D Summary of contents
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... Hardware watchdog timer, power fail monitor • LCD driver with 4 common segment drivers 156 (71M6531D/F) or 268 pixels (71M6532D/F) • (71M6531D/ (71M6532D/F) general-purpose I/O pins. Digital I/O pins compatible with 5 V inputs • 32 kHz time base • High-speed slave SPI interface to data RAM • ...
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... Delay Compensation ..................................................................................................... 17 1.2.15 CE Functional Overview ................................................................................................ 17 1.3 80515 MPU Core ....................................................................................................................... 19 1.3.1 Memory Organization and Addressing .......................................................................... 19 1.3.2 Special Function Registers (SFRs) ............................................................................... 21 1.3.3 Generic 80515 Special Function Registers ................................................................... 22 1.3.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F ..... 24 1.3.5 Instruction Set ................................................................................................................ 26 1.3.6 UARTs ........................................................................................................................... 26 1.3.7 Timers and Counters ..................................................................................................... 28 1.3.8 WD Timer (Software Watchdog Timer) ......................................................................... 30 1.3.9 Interrupts ........................................................................................................................ 30 1.4 On-Chip Resources ...
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... I/O RAM and SFR Map – Functional Order ............................................................................... 72 4.2 I/O RAM Description – Alphabetical Order ................................................................................ 77 4.3 CE Interface Description ............................................................................................................ 88 4.3.1 CE Program ................................................................................................................... 88 4.3.2 CE Data Format ............................................................................................................. 88 4.3.3 Constants ....................................................................................................................... 88 4.3.4 Environment ................................................................................................................... 88 4.3.5 CE Calculations ............................................................................................................. 89 4.3.6 CE Status and Control ................................................................................................... 89 4.3.7 CE Transfer Variables ................................................................................................... 92 4.3.8 Pulse Generation ........................................................................................................... 93 4.3.9 CE Calibration Parameters ............................................................................................ 94 v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 3 ...
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... Typical Performance Data ....................................................................................................... 107 5.6.1 Accuracy over Current ................................................................................................. 107 5.6.2 Accuracy over Temperature ........................................................................................ 107 5.7 71M6531D/F Package ............................................................................................................. 108 5.7.1 Package Outline .......................................................................................................... 108 5.7.2 71M6531D/F Pinout (QFN-68) ..................................................................................... 109 5.7.3 Recommended PCB Land Pattern for the QFN-68 Package ...................................... 110 5.8 71M6532D/F Package ............................................................................................................. 111 5.8.1 71M6532D/F Pinout (LQFP-100) ................................................................................. 111 5.8.2 LQFP-100 Mechanical Drawing ................................................................................... 112 5 ...
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... FDS 6531/6532 005 Figures Figure 1: 71M6531D/F IC Functional Block Diagram ................................................................................... 8 Figure 2: 71M6532D/F IC Functional Block Diagram ................................................................................... 9 Figure 3: General Topology of a Chopped Amplifier .................................................................................. 13 Figure 4: CROSS Signal with CHOP_E[1: ....................................................................................... 13 Figure 5: AFE Block Diagram (Shown for the 71M6532D/F) ...................................................................... 14 Figure 6: Samples from Multiplexer Cycle .................................................................................................. 18 Figure 7: Accumulation Interval .................................................................................................................. 18 Figure 8: Interrupt Structure ...
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... Table 39: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6531D/F) ......................... 42 Table 40: Data/Direction Registers and Internal Resources for DIO 17-29 (71M6531D/F) ....................... 42 Table 41: Data/Direction Registers and Internal Resources for DIO 43-46 (71M6531D/F) ....................... 42 Table 42: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6532D/F) ......................... 43 Table 43: Data/Direction Registers and Internal Resources for DIO 16-30 (71M6532D/F) ....................... 43 Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F) ...
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... Table 86: RESET Timing .......................................................................................................................... 105 Table 87: SPI Slave Port (MISSION Mode) Timing .................................................................................. 106 Table 88: Recommended PCB Land Pattern Dimensions ........................................................................ 110 Table 89: Power and Ground Pins ............................................................................................................ 113 Table 90: Analog Pins ............................................................................................................................... 113 Table 91: Digital Pins ................................................................................................................................ 114 v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 7 ...
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... SENSOR RTC_MIN RTC_MO RTC_SEC RTC_YR TEST TEST MODE MPU RX UART1 FAULTZ V1 POWER FAULT RESET Figure 1: 71M6531D/F IC Functional Block Diagram 8 © 2005-2010 TERIDIAN Semiconductor Corporation GNDD GNDA ∆Σ ADC CONVERTER VBIAS CE FIR RTM FIR_LEN PLS_INV 22 PLS_INTERVAL PLS_MAXWIDTH RPULSE CE_LCTN ADC_E ...
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... EEDATA EECTRL UART2--OPTICAL OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV OPT_TXMOD OPT_FDC NVRAM GP0-GP7 EMULATOR 8 IRAM BUS ICE_E IRAM 256B ICE_E Data Sheet 71M6531D/F-71M6532D/F V3P3A V3P3SYS V3P3D VBAT to TMUX VOLT REG LCD_ONLY SLEEP V2P5 2.5V to logic 2.5V_NV DIO_PV DIO_PW DIO_PX DIO_PY DIO47/SEG67...DIO51/SEG71 5 DIO40/SEG60 ...
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... Signal Input Pins All analog signal input pins are sensitive to voltage. In the 71M6531D/F, the VA and VB pins, as well as the IA and IB pins are single-ended. In the 71M6532D/F, the IAP/IAN and IBP/IBN pins can be programmed individually to be differential (see I/O RAM bit SEL_IAN and SEL_IBN) or single-ended. The differential signal is applied between the IAP and IAN input pins and between the IBP and IBN input pins ...
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... SLOT3_ALTSEL[3:0] – – SLOT4_ALTSEL[3:0] – – SLOT5_ALTSEL[3:0] – – SLOT6_ALTSEL[3:0] – – SLOT7_ALTSEL[3:0] – – SLOT8_ALTSEL[3:0] – – SLOT9_ALTSEL[3:0] Data Sheet 71M6531D/F-71M6532D prevent Alternate Slot Typical Selections RAM Signal for Address ADC A TEMP VBAT 3 VA – – – ...
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... CK32 rising edge to increment its state and initiate the next FIR conversion. FIR conversions require CK32 cycles. The number of CK32 cycles is determined by FIR_LEN[1:0], as shown in 1.2.3 A/D Converter (ADC) A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6531D/F and 71M6532D/F. The resolution of the ADC is programmable using the I/O RAM M40MHZ and M26MHZ bits (see Table 2) ...
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... CROSS over two accumulation interval when CHOP_E[1:0] = 00: At the end of the first interval, CROSS is low, at the end of the second interval, CROSS is high. The offset error for the two temperature measurements taken during the ALT multiplexer frames will be averaged to zero. Note that v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D ...
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... CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals. Figure 5 shows the block diagram of the AFE, with current inputs shown only as differential pair of pins (for the 71M6531D/F, the current input for phase single pin [IA]). IAP IAN VA ...
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... PRE_SAMPS[1:0] * SUM_CYCLES[5:0]/2520.6 (with MUX_DIV[3:0] = 1). The CE hardware issues the XFER_BUSY interrupt when the accumulation is complete. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Name Description 0x00 IA Phase A current 0x01 VA Phase A voltage 0x02 IB Phase B current 0x03 VB Phase B voltage – Not used 0x0A TEMP Temperature 0x0B VBAT Battery Voltage Data Sheet 71M6531D/F-71M6532D/F 15 ...
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... Data Sheet 71M6531D/F-71M6532D/F 1.3.1 Meter Equations The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM location EQU[2:0] (equation assist). The Compute Engine (CE) firmware for residential configurations implements the equations listed in EQU[2:0] specifies the equation to be used based on the number of phases used for metering. ...
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... PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6, where 2520.6 is the sample rate [Hz] v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation the MUX frame completes. For instance, if the CE code outputs = ⋅ ⋅ 360 delay is the sampling delay between voltage and current. delay Data Sheet 71M6531D/F-71M6532D/F Figure 6 shows the timing of the 17 ...
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... Data Sheet 71M6531D/F-71M6532D/F For example, PRE_SAMPS[1: and SUM_CYCLES[5: will establish 2100 samples per accumulation cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5: will result in the exact same accumulation cycle of 2100 samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available. ...
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... MPU Core The 71M6531D/F and 71M6532D/F include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 10-MHz clock results in a processing throughput of 10 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases ...
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... Data Sheet 71M6531D/F-71M6532D/F The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction). Internal and External Memory Map Table 7 shows the address, type, use and size of the various memory components ...
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... SFRs specific to the 71M6531D/F and 71M6532D/F are shown in bold print on a gray field. The registers at 0x80, 0x88, 0x90, etc., are bit addressable, all others are byte addressable. See the restrictions for the ...
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... Data Sheet 71M6531D/F-71M6532D/F 1.4.3 Generic 80515 Special Function Registers Table 10 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table. Table 10: Generic 80515 SFRs - Location and Reset Values ...
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... Writing a 0 causes the corresponding pin to be held at a low level (GND). The data direction registers DIR0, DIR1 and DIR2 define individual pins as input or output pins (see Sections 1.5.7 Digital I/O – 71M6531D/F v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Function F0 is not to be confused with the F0 flag in the CESTATUS register ...
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... Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F Table 14 shows the location and description of the SFRs specific to the 71M6531D/F and 71M6532D/F. Table 14: 71M6531D/F and 71M6532D/F Specific SFRs Register SFR (Alternate Name) Address 0x9E EEDATA EECTRL ...
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... Only byte operations on the entire INTBITS register should be used when writing. The byte must have all bits set except the bits that are to be cleared. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Bit Field R/W Name This register is used to initiate either the Flash W Mass Erase cycle or the Flash Page Erase cycle ...
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... UART0 TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6531D/F and 71M6532D/F have several UART-related registers for the control and buffering of serial data. A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1) ...
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... In Mode 1, SM20 is 0, Function SM Mode Description 0 A 9-bit UART 1 B 8-bit UART th transmitted data bit in Mode A. Set or cleared by the MPU, Data Sheet 71M6531D/F-71M6532D/F th bit set additional Table 19. . The hardware implements SM0 SM1 ...
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... Data Sheet 71M6531D/F-71M6532D/F Bit Symbol In Modes A and the 9 S1CON[2] RB81 RB81 is the stop bit. Must be cleared by software Transmit interrupt flag, set by hardware after completion of a serial transfer. S1CON[1] TI1 Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. ...
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... IE0 pin int0 is observed. Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on TCON[0] IT0 input pin to cause interrupt. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Timer 1 Mode 0 Mode 1 Yes Yes Yes Yes ...
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... Data Sheet 71M6531D/F-71M6532D/F 1.4.8 WD Timer (Software Watchdog Timer) There is no internal software watchdog timer. Use the standard watchdog timer instead (see Hardware Watchdog Timer). 1.4.9 Interrupts The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON and SCON) ...
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... External interrupt 5 occurred and has not been cleared. IRCON[3] IEX4 1 = External interrupt 4 occurred and has not been cleared. IRCON[2] IEX3 1 = External interrupt 3 occurred and has not been cleared. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Function Function Function Function Function 31 ...
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... External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6531D/F or 71M6532D/F, for example the CE, DIO, RTC or EEPROM interface. The external interrupts are connected as described in programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0) ...
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... Level 0 (lowest Level Level Level 3 (highest) Data Sheet 71M6531D/F-71M6532D/F Interrupt Description External interrupt 4 External interrupt 5 External interrupt 6 XFER_BUSY interrupt (INT 6) RTC_1SEC interrupt (INT 6) WDT near overflow (INT 6) SPI Interface (INT2) FWCOL0 interrupt (INT 2) FWCOL1 interrupt (INT 2) PLL_OK rise interrupt (INT 4) PLL_OK fall interrupt (INT 4) † ...
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... Data Sheet 71M6531D/F-71M6532D/F Table 34: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) – IP0 SFR 0xA9 – SFR 0xB9 IP1 Interrupt Sources and Vectors Table 36 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag ...
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... IE_RTC WD_NROVF_FLAG Figure 8: Interrupt Structure © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D ...
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... Oscillator The oscillator of the 71M6531D/F and 71M6532D/F drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The oscillator of the 71M6531D/F and 71M6532D/F has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. ...
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... MPU firmware can treat them as a single register. A single binary number can be calculated and then loaded into them at the same time. The 71M6531D/F and 71M6532D/F have two rate adjustment mechanisms. The first is an analog rate adjustment, using RTCA_ADJ[6:0], which trims the crystal load capacitance. Setting RTCA_ADJ[6: minimizes the load capacitance, maximizing the oscillator frequency ...
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... Physical Memory Flash Memory The 71M6531D and 71M6532D include 128 KB of on-chip flash memory. The 71M6531F and 71M6532F offer 256 KB of flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE and MPU data in RAM, as well as of I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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... KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is banked using the I/O RAM FL_BANK register as follows: • The 71M6531D provides 4 banks each selected by FL_BANK[1:0]. Note that when FL_BANK[1:0] = 00, the upper bank is the same as the lower bank. • ...
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... Write operations to page zero, whether by MPU or ICE are inhibited. MPU/CE RAM: The 71M6531D/F and 71M6532D/F include static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the MPU core. The static RAM are used for data storage for MPU and CE operations ...
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... A B 1.5.7 Digital I/O – 71M6531D/F The 71M6531D/F includes pins of general-purpose digital I/O. These pins are compatible with 5 V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows: • Dedicated DIO pins (1 pin): PB • DIO/LCD segment pins (a total of 19 pins): ...
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... Data Register DIO2 = P2 (SFR 0xA0) – 1 Direction Register 0 = input, DIO_DIR2 (SFR 0xA1 output Table 41: Data/Direction Registers and Internal Resources for DIO 43-46 (71M6531D/F) DIO LCD Segment Pin number Configuration (DIO or LCD segment) Data Register Direction Register 0 = input output 42 © 2005-2010 TERIDIAN Semiconductor Corporation 2 – ...
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... LCD_BITMAP[47:40 – – – Data Sheet 71M6531D/F-71M6532D 100 LCD_BITMAP[39:32 DIO1 = P1 (SFR 0x90) 1 ...
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... DIO_DIR58[7] and with DIO_56[4] through DIO_58[4] in I/O RAM. 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO ...
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... HIGH-Z LOW Figure 10: Connecting an External Load to DIO Pins 1.5.10 LCD Drivers – 71M6531D/F The 71M6531 contains a total of 39 dedicated and multiplexed LCD drivers which are grouped as follows: • 11 dedicated LCD segment drivers – always available • 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX) – available in normal operation mode (when not emulating) • ...
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... The same value can also be a calibration offset for any battery voltage display. See Section 5.4.4 Battery Monitor 1.5.14 EEPROM Interface The 71M6531D/F and 71M6532D/F provide hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication. 46 © 2005-2010 TERIDIAN Semiconductor Corporation Order. The LCD drivers are supported by the four common 1.5.8 Digital I/O – ...
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... Positive CMD[3:0] 0000 0010 0011 0101 0110 1001 Others Data Sheet 71M6531D/F-71M6532D/F Operation 2 No-op command. Stops the I C clock (SCK, DIO4). If not issued, SCK keeps toggling. Receive a byte from the EEPROM and send ACK. Transmit a byte to the EEPROM. Issue a STOP sequence. ...
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... Data Sheet 71M6531D/F-71M6532D/F Table 48: EECTRL Bits for the 3-Wire Interface Control Read/ Name Bit Write 7 WFR W Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence ...
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... SDATA (output) SDATA output Z BUSY (bit) CNT Cycles (6 shown (From 6520) (LoZ) and in Figure 16 illustrate the SPI Interface read and write timing. Data Sheet 71M6531D/F-71M6532D/F INT5 INT5 not issued CNT Cycles (0 shown) (HiZ) INT5 D3 D2 BUSY ...
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... Data Sheet 71M6531D/F-71M6532D/F Command 11xx xxxx ADDR Byte0 ... ByteN 10xx xxxx ADDR Byte0 ... ByteN Certain I/O RAM registers can be written and read using the SPI port (see Table 50). However, the MPU takes priority over the I/O RAM bus, and SPI operation may fail without notice. To avoid this situation, the SPI host should send a command other than 11xxxxxx or 10xxxxxx (read or write) before the actual read or write command ...
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... MPU, I/O RAM, but not SFRs or the 80515-internal register bank communication link can be established via the SPI interface: By writing into MPU memory locations, the external host can initiate and control processes in the MPU of the 71M6531D/F or 71M6532D/F. Writing MPU location normally generates an interrupt, a function that can be used to signal to the MPU that the byte that had just been written by the external host must be read and processed ...
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... Data Sheet 71M6531D/F-71M6532D/F 1.5.16 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included V1 in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every V3P3 WDT dis- V3P3 - 10mV abled 1 ...
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... The TMUXOUT pin may be used for diagnosis purposes or in production test. The RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides even higher precision. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Table 51 can be selected to be output on the TMUXOUT pin. Table 51: TMUX[4:0] Selections ...
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... Data Sheet 71M6531D/F-71M6532D/F 2 Functional Description 2.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh cos φ* t Reactive Energy [VARh sin φ ...
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... ADC MUX Frame MUX_DIV=4 (4 conversions) is shown 1 ADC0 ADC1 450 900 INITIATED OPCODE AT END OF SUMMATION INTERVAL FLAG FLAG Figure 20: RTM Output Format Data Sheet 71M6531D/F-71M6532D/F Settle 2 3 ADC2 ADC3 1350 1800 MAX CK COUNT ...
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... Data Sheet 71M6531D/F-71M6532D/F 2.3 Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. ...
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... Yes Yes Yes Yes Yes – Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Data Sheet 71M6531D/F-71M6532D/F Table 52 shows LCD SLEEP – – – – – – – – – – – – – – ...
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... Data Sheet 71M6531D/F-71M6532D/F can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically transition from any of the battery modes to MISSION mode, once the PLL has settled. The MPU will run at 7/8 of the crystal clock rate. This permits the UARTs to be operated at 300 bd. In this mode, the MPU clock has substantial short-term jitter ...
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... Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Transition MISSION 13..14 CK cycles Xtal 2048...4096 CK32 cycles BROWN- MISSION OUT Xtal 14.5 CK32 cycles 4096 CK32 cycles 1024 CK32 cycles Data Sheet 71M6531D/F-71M6532D/F 300nA PLL (4.2MHz/MUX_DIV) time 300nA PLL (4.2MHz) time 59 ...
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... Power Fault Circuit The 71M6531D/F and 71M6532D/F include a comparator to monitor system power fault conditions. When the output of the comparator falls (V1<VBIAS), the I/O RAM bits PLL_OK are zeroed and the part switches to BROWNOUT mode if a battery is present. Once system power returns, the MPU remains in reset and does not transition to MISSION mode until 2048 to 4096 CK32 clock cycles later, when PLL_OK rises ...
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... These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. Figure 26 illustrates the CE/MPU data flow. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 15 CK32 cycles BROWNOUT Figure 25: Wake Up Timing time ...
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... Data Sheet 71M6531D/F-71M6532D/F Samples 2.7 CE/MPU Communication Figure 27 shows the functional relationships between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as external interrupts ...
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... R Figure 30: Resistive Shunt (Left) and Rogowski Sensor (Right) Connection 3.2 Connecting 5-V Devices All digital input pins of the 71M6531D/F and 71M6532D/F are compatible with external 5-V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation ...
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... Data Sheet 71M6531D/F-71M6532D/F 3.3 Temperature Measurement Measurement of absolute temperature uses the on-chip temperature sensor and applying the following formula: In the above formula the temperature in °C, N(T) is the ADC count at temperature T, N count at 25° the sensitivity in LSB/°C as stated in the Electrical Specifications and T ...
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... RTC time can be calculated and applied to the RTC after main power returns to the meter. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation ±40 PPM/°C ±40 PPM/° ⋅ TEMP _ X PPMC = + + 16385 14 2 Data Sheet 71M6531D/F-71M6532D ⋅ 2 TEMP _ X PPMC ...
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... The 71M6531D/F and 71M6532D/F have an on-chip LCD controller capable of controlling static or multiplexed LCDs. Figure 32 shows the basic connection for an LCD. The following dedicated and multi-use pins can be assigned as LCD segment pins for the 71M6531D/F: • 12 dedicated LCD segment pins: SEG0 to SEG2, SEG7, SEG8, SEG12 to SEG18. • ...
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... UART1. The OPT_TX pin becomes active when the I/O RAM register OPT_TXE is set to 00. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 71M653X V3P3D DIO4 DIO5 DIOn 100 kΩ 100 kΩ 35 Ω 100 Figure 35: Connections for UART0 Data Sheet 71M6531D/F-71M6532D/F EEPROM VCC CLK Ω Figure 36 shows the basic connections 67 ...
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... With modulation, an optical emitter can be operated at higher current than nominal, enabling it to increase the distance along the optical path. If operation in BROWNOUT mode is desired, the external components should be connected to V3P3D. 71M6531D/F or 71M6532D/F OPT_RX OPT_TX Figure 36: Connection for Optical Components 3 ...
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... V3P3D 71M6531D/F 71M6532D/F RESET 10k Ω GNDD 39. Production boards should have the ICE_E pin connected to ground. LCD Segments (optional Data Sheet 71M6531D/F-71M6532D/F 71M6533 71M6533 71M6531D/F 71M6532D/F RESET RESET 100Ω 100Ω DGND DGND ...
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... All application-specific MPU functions mentioned in the demonstration source code supplied by Teridian. The code is available as part of the Demonstration Kit for the 71M6531D/F and 71M6532D/F. The Demonstration Kits come with the 71M6531D/F or 71M6532D/F preprogrammed with demo firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE) ...
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... FDS 6531/6532 005 3.17 Meter Calibration Once the Teridian 71M6531D/F or 71M6532D/F energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF). ...
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... Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the VBAT pin. This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with † apply to the 71M6531D/F only, bits marked with ‡ apply to the 71M6532D/F only and should be 0 for the other device. ...
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... DIO_DIR2[5] DIO_DIR2[4] DIO_DIR2[3] DIO_3[5] DIO_3[4]† U RTCA_ADJ[6:0] SUBSEC[7: RTC_YR[7:0] U PREG[13:6] PREG[5:0] RTC write protect register © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Bit 3 Bit 2 Bit 1 DIO_RRX[2:0] DIO_PW DIO_PV OPT_TXMOD U DI_RPB[2:0] U DIO_R2[2:0] U DIO_R4[2:0] U DIO_R6[2:0] U DIO_R8[2:0] U DIO_R10[2:0] ...
Page 74
... Data Sheet 71M6531D/F-71M6532D/F Name Addr Bit 7 LCD Display Interface: 2020 MUX_SYNC_E LCDX 2021 U LCDY LCD_MAP0 2023 LCD_BITMAP LCD_BITMAP LCD_MAP1 2024 [39]‡ 2025 LCD_MAP2 LCD_MAP3 2026 LCD_BITMAP LCD_BITMAP 2027 LCD_MAP4 [63] LCD_BITMAP LCD_BITMAP LCD_MAP5 2028 [71]‡ 2029 LCD_MAP6 LCD0 2030 2031 LCD1 ...
Page 75
... U RTM1[7:0] U RTM2[7:0] U RTM3[7:0] SP_CMD[7:0] SP_ADDR[15:8] SP_ADDR[7:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] SLOT1_SEL SLOT3_SEL © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Bit 3 Bit 2 Bit 1 LCD_SEG27[3:0]† LCD_SEG28[3:0] LCD_SEG29[3:0] LCD_SEG30[3:0] … LCD_SEG35[3:0] LCD_SEG36[3:0]‡ LCD_SEG37[3:0] LCD_SEG38[3:0]‡ … LCD_SEG41[3:0]‡ LCD_BLKMAP18[3:0] RTM0[9:8] RTM1[9:8] ...
Page 76
... SPI Interrupt: 20B0 SPI0 20B1 SPI1 General-Purpose Nonvolatile Registers: GP0 20C0 … … 20C7 GP7 VERSION 20C8 Serial EEPROM: SFR 9E EEDATA SFR 9F EECTRL † 71M6531D/F only ‡ 71M6532D/F only 76 Bit 6 Bit 5 Bit 4 SLOT1_ALTSEL SLOT3_ALTSEL IEN_SPI U SPI_FLAG GPO[7:0] … GP7[7:0] VERSION[7:0] ...
Page 77
... This bit must be set to enable chop mode for the current channels (71M6532D/F only). Control bit for the SEG19/CKOUT pin: 0 R/W 0: The pin is the SEG19 LCD driver 1: The pin is the CK_FIR output (5 MHz in mission mode, 32 kHz in brownout mode) © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Description 77 ...
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... Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake COMP_STAT[0] 2003[0] – 2009[2:0] 0 DI_RPB[2:0] DIO_R1[2:0] 2009[6:4] 0 DIO_R2[2:0] 200A[2:0] 0 DIO_R4[2:0] 200B[2:0] 0 DIO_R5[2:0] 200B[6:4] 0 DIO_R6[2:0] 200C[2:0] 0 DIO_R7[2:0] 200C[6:4] 0 DIO_R8[2:0] 200D[2:0] 0 DIO_R9[2:0] 200D[6:4] 0 DIO_R10[2:0] 200E[2:0] 0 DIO_R11[2:0] 0 200E[6:4] DIO_RRX[2:0] 20AF[2:0] 0 SFR A2 [7:1] 0 DIO_DIR0[7:1] DIO_DIR1[7:0] SFR 91 0 DIO_DIR2[1] ...
Page 79
... Flash bank. Memory above mapped to the MPU address space from 0x8000 1 R/W to 0xFFFF banks. When MPU address[15 the address in flash is mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle. © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Description Resulting FIR Resulting Filter Cycles CK32 Cycles ...
Page 80
... Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake FLSH_ERASE SFR 94[7:0] 0 [7:0] SFR B2[1] 0 FLSH_MEEN FLSH_PGADR SFR B7 [7:2] 0 [5:0] SFR B2[0] 0 FLSH_PWE 20C0 0 GP0 … … … 20C7 0 GP7 IE_FWCOL0 SFR E8[2] 0 IE_FWCOL1 SFR E8[3] 0 SFR E8[4] 0 IE_PB SFR E8[6] 0 IE_PLLRISE IE_PLLFALL SFR E8[7] 0 IEN_SPI 20B0[ Dir Flash Erase Initiate. (Default = 0x00). FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle ...
Page 81
... TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Description Table 54 for bit availability. Table 54 for bit availability. Table 54 for bit availability. Table 54 for bit availability. Table 54 for bit availability. frame rate) according to the ...
Page 82
... Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake LCD_DAC[2:0] 20AB[3:1] 0 LCD_E 2021[5] 0 LCD_MODE[2:0] 2021[4:2] 0 LCD_ONLY 20A9[5] 0 2030[3:0] 0 LCD_SEG0[3:0] … … … 2043[3:0] 0 LCD_SEG19[3:0] LCD_SEG24[3:0] 2048[3:0] 0 … … … LCD_SEG31[3:0] 204F[3:0] 0 LCD_SEG32[3:0] 2050[3: Dir LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS (mission mode) or VBAT (brownout/LCD modes) ...
Page 83
... The MPU clock divider (from MCK). These bits may be programmed by MPU without risk of losing control. Resulting Clock Frequency MPU_DIV[2:0] 2 000 MCK/2 3 001 MCK R/W 010 MCK/2 5 011 MCK/2 6 100 MCK/2 7 101 MCK/2 8 110 MCK/2 8 111 MCK/2 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Description 83 ...
Page 84
... Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake MUX_ALT 2005[2] 0 MUX_DIV[3:0] 209D[3:0] 0 2020[7] 0 MUX_SYNC_E 2007[1:0] 0 OPT_FDC[1:0] OPT_RXDIS 2008[5] 0 2008[4] 0 OPT_RXINV OPT_TXE[1:0] 2007[7:6] 00 2008[0] 0 OPT_TXINV OPT_TXMOD 2008[1] 0 PLL_OK 2003[6] 0 PLS_MAXWIDTH 2080[7:0] FF [7:0] PLS_INTERVAL 2081[7:0] 0 [7:0] 84 Dir The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an alternate set of inputs ...
Page 85
... The four RTM probes. Before each CE code pass, the values of these registers are R/W 0 serially output on the RTM pin. The RTM registers are ignored when RTM_E = © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Description for additional details 100 for additional details. ...
Page 86
... Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake SFRB2[6] 0 SECURE 20AC[1] 0 SEL_IAN 20AC[5] 0 SEL_IBN SLEEP 20A9[6] 0 2090[3:0] 0 SLOT0_SEL[3:0] SLOT1_SEL[3:0] 2090[7:4] 1 SLOT2_SEL[3:0] 2091[3:0] 2 SLOT3_SEL[3:0] 2091[7:4] 3 SLOT0_ALTSEL 2096[3:0] A [3:0] SLOT1_ALTSEL 2096[7:4] 1 [3:0] 2097[3:0] 2 SLOT2_ALTSEL [3:0] SLOT3_ALTSEL 2097[7:4] 3 [3:0] SP_ADDR[15:8] 2072[7:0] 0 2073[7:0] 0 SP_ADDR[7:0] SP_CMD 2071 0 SPE 2070[7] 0 SPI_FLAG ...
Page 87
... When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page 0 erase. When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory 0 from flash page erase. © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Description Purpose Trim for the magnitude of VREF 87 ...
Page 88
... Data Sheet 71M6531D/F-71M6532D/F 4.3 CE Interface Description 4.3.1 CE Program The CE performs the precision computations necessary to accurately measure energy. Different code variations are used for EQU[2: and EQU[2: The computations include offset cancellation, products, product smoothing, product summation, frequency detection, VAR calculation, sag detection, peak detection and voltage phase measurement ...
Page 89
... TERIDIAN Semiconductor Corporation Element Input Mapping W0SUM/ W1SUM/ VAR0SUM VAR1SUM φ ) VA*IA VA*IB VA*(IA-IB)/2 (VA * IB)/2 φ ) VA*IA VB*IB φ the derived clock operating at the fundamental input 0 Description See description of CESTATUS bits in Data Sheet 71M6531D/F-71M6532D/F Figure 19). This means that I0SQSUM I1SQSUM IA IB IA- Table 57. Table 57. 89 ...
Page 90
... Data Sheet 71M6531D/F-71M6532D/F Table 57: CESTATUS (CE RAM 0x80) Bit Definitions CESTATUS [bit] Name 31:29 Not Used Reserved 26 SAG_B 25 SAG_A 24:0 Not Used The CE is initialized and its functions are controlled by the MPU using CECONFIG. This register contains in packed form SAG_CNT, FREQSEL, EXT_PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW and PULSE_FAST. ...
Page 91
... The threshold for sag warnings. The default value is 443000 equivalent RMS if VMAX = 600 V. The LSB value is VMAX * 4.255*10 Table 60: Gain Adjust Control Default This register scales all voltage and current channels. The 16384 default value is equivalent unity gain (1.000). Data Sheet 71M6531D/F-71M6532D/F Description ...
Page 92
... Data Sheet 71M6531D/F-71M6532D/F 4.3.7 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of CE transfer variables always end with _X ...
Page 93
... Scales all voltage and current inputs. A value of 16384 provides unity gain. This register is used by the the MPU to 16384 implement temperature compensation. Output of the battery measurement. This value is equivalent to N/A twice the measured ADC value. Data Sheet 71M6531D/F-71M6532D In_8 ...
Page 94
... Data Sheet 71M6531D/F-71M6532D/F The maximum time jitter is 67 µs and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any rollover characteristics ...
Page 95
... Text strings holding the CE version information as supplied by the CE data associated with the CE code. For example, the words 0x63653331 and 0x61303463 form the text string “ce31a04c”. These locations are overwritten in operation. Data Sheet 71M6531D/F-71M6532D/F Description ⋅ Φ TAN at 60Hz ⋅ ...
Page 96
... Data Sheet 71M6531D/F-71M6532D/F Figure 41: CE Data Flow: Multiplexer and ADC Figure 42: CE Data Flow: Scaling, Gain Control, Intermediate Variables 96 © 2005-2010 TERIDIAN Semiconductor Corporation FDS 6531/6532 005 v1.3 ...
Page 97
... FDS 6531/6532 005 Figure 43: CE Data Flow: Squaring and Summation Stages v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 97 ...
Page 98
... Data Sheet 71M6531D/F-71M6532D/F 5 Electrical Specifications 5.1 Absolute Maximum Ratings Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (Section 5 ...
Page 99
... V3P3A and V3P3SYS must be at the same voltage VBAT Operating Temperature v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Function Bypass capacitor for 3.3 V supply Bypass capacitor for 3.3 V output Bypass capacitor for V3P3SYS Bypass capacitor for V2P5 32.768 kHz crystal – electrically similar to ECS ...
Page 100
... Data Sheet 71M6531D/F-71M6532D/F 5.4 Performance Specifications 5.4.1 Input Logic Levels Parameter a Digital high-level input voltage a Digital low-level input voltage , V Input pull-up current E_RXTX, E_RST, CKTEST Other digital inputs Input pull down current ICE_E RESET PB Other digital inputs a In battery powered modes, digital inputs should be below 0 above 2 minimize battery current. ...
Page 101
... Iload = 0 Iload = Iload = 5 mA, reduce V3P3 until V2P5 drops 200 mV RESET=0, iload=0 Condition LOAD LOAD mA, reduce VBAT LOAD until REG_LP_OK = LOAD Data Sheet 71M6531D/F-71M6532D/F Min Typ Max 4.2 6.35 8.4 9.6 3.3 3.8 -400 +400 9 250 82 250 11 ...
Page 102
... Data Sheet 71M6531D/F-71M6532D/F 5.4.9 Crystal Oscillator Table 78: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal 1 XIN to XOUT Capacitance 1 Capacitance to GNDD XIN XOUT 5.4.10 LCD DAC Table 79: LCD DAC Performance Specifications Parameter VLCD Voltage = ⋅ − ⋅ 059 LCD_DAC) LCD 5 ...
Page 103
... Condition Ta = 22ºC V3P3A = 3.0 to 3.6 V VREF_DIS = 1, VREF = 1.3 to 1.7 V CAL = µA, -10 µA LOAD = + VNOM ( T ) VREF ( Data Sheet 71M6531D/F-71M6532D/F Min Typ Max -106 -964 -2286 LSB/ºC -260 -2286 -8207 49447 449446 1065353 121071 1065353 3825004 -10 10 Min Typ Max 1 ...
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... Data Sheet 71M6531D/F-71M6532D/F Parameter VNOM temperature coefficients: TC1 TC2 VREF(T) deviation from VNOM(T) − 6 VREF ( T ) VNOM ( − VNOM ( T ) max VREF aging a This relationship describes the nominal behavior of VREF at different temperatures. 5.4.15 ADC Converter, V3P3A Referenced Table 84 shows the performance specifications for the ADC converter, V3P3A referenced. For this data, FIR_LEN[1:0]=0, VREF_DIS=0 and LSB values do not include the 8-bit left shift at the CE input ...
Page 105
... Mode) -40°C to +85°C 25°C 85°C Table 86: EEPROM Interface Timing Condition CKMPU = 4.9 MHz, Using interrupts CKMPU = 4.9 MHz, bit-banging DIO4/5 CKMPU=4.9 MHz Table 87: RESET Timing Condition Condition Data Sheet 71M6531D/F-71M6532D/F Min Typ Max 30 100 20,000 Cycles 100 Years 10 Years 2 Cycles ...
Page 106
... Data Sheet 71M6531D/F-71M6532D/F 5.5.5 SPI Slave Port (MISSION Mode) Table 88: SPI Slave Port (MISSION Mode) Timing Parameter t PCLK cycle time SPIcyc t Enable lead time SPILead t Enable lag time SPILag t PCLK pulse width: SPIW High Low t PCSZ to first PCLK fall SPISCK t Disable time ...
Page 107
... Accuracy over Temperature With digital temperature compensation enabled, the temperature characteristics of the reference voltage (VREF) are compensated to within ±40 PPM/°C (see section 3.4 for details). v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 6531 Wh, All Phases, 50 Hz, 240 V 10 100 I (A rms) ...
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... Data Sheet 71M6531D/F-71M6532D/F 5.7 71M6531D/F Package 5.7.1 Package Outline PIN #1 DOT MARKING 0.850 ±0.050 Figure 46: QFN-68 Package Outline, Top and Side View 0.400 ±0.050 0.200 ±0.050 PIN #1 ID R0.20, or CHAMFER 0.500 x 45° Figure 47: QFN-68 Package Outline, Bottom View * Pin length is nominally 0.4 mm (min = 0.3 mm, max = 0.4 mm). ...
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... FDS 6531/6532 005 5.7.2 71M6531D/F Pinout (QFN-68) GNDD 1 SEG9/E_RXTX 2 DIO2/OPT_TX 3 TMUXOUT 4 SEG66/DIO46 SEG3/PCLK 7 V3P3D 8 SEG19/CKTEST 9 V3P3SYS 10 SEG4/PSDO 11 SEG5/PCSZ 12 SEG37/DIO17 13 COM0 14 COM1 15 COM2 16 COM3 17 v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation TERIDIAN 71M6531D-IM 71M6531F-IM Figure 48: Pinout for QFN-68 Package Data Sheet 71M6531D/F-71M6532D/F RESET ...
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... Data Sheet 71M6531D/F-71M6532D/F 5.7.3 Recommended PCB Land Pattern for the QFN-68 Package Figure 49: PCB Land Pattern for QFN 68 Package Table 89: Recommended PCB Land Pattern Dimensions Symbol Notes not place unmasked vias in the region denoted by dimension d. 2. Soldering of bottom internal pad is not required for proper operation. ...
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... DIO57 15 DIO58 16 DIO3 17 COM0 18 COM1 19 COM2 20 COM3 21 SEG67/DIO47 22 SEG68/DIO48 23 SEG69/DIO49 24 SEG70/DIO50 25 Figure 50: PCB Land Pattern for LQFP-100 Package v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F Teridian 71M6532D 71M6532F GNDD 75 RESET 74 V2P5 73 VBAT SEG31/DIO11 70 SEG30/DIO10 69 SEG29/DIO9/YPULSE 68 SEG28/DIO8/XPULSE 67 SEG41/DIO21 66 SEG40/DIO20 ...
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... Data Sheet 71M6531D/F-71M6532D/F 5.8.2 LQFP-100 Mechanical Drawing 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 51: LQFP-100 Package, Mechanical Drawing 112 © 2005-2010 TERIDIAN Semiconductor Corporation 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 TYP. 0.10 +/- 0.10 Side View (Dimensions are in mm.) FDS 6531/6532 005 0.60 TYP> v1.3 ...
Page 113
... If an external clock is used, a 150 mV (p-p) clock signal should be applied to XIN, and XOUT should be left unconnected. 1) Differential pin pairs IAP/IAN and IBP/IBN, as well as single-ended VX pin used on 71M6532D/F only. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Table 90: Power and Ground Pins Description Table 91: Analog Pins Description Data Sheet 71M6531D/F-71M6532D/F 5.9.4 I/O Equivalent Circuits. 113 ...
Page 114
... TEST Not all pins available on the 71M6531D/F or 71M6532D/F. 114 © 2005-2010 TERIDIAN Semiconductor Corporation Table 92: Digital Pins Description LCD Common Outputs: These 4 pins provide the select signals for the LCD display. Dedicated LCD Segment Output pins. Dedicated LCD Segment Output pins (71M6532D/F only). ...
Page 115
... Output Pin GNDD GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F LCD SEG LCD Output Driver Pin GNDD LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG ...
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... LQFP, lead free 71M6532F 71M6532F 7 Related Information The following documents applicable to the 71M6531D/F and 71M6532D/F are available from Teridian Semiconductor Corporation: • 71M653X Software User’s Guide (SUG_653X) • Demo Board User’s Guide (DBUM_6531) • Application Note on Migration from the 6521 to the 6531 (AN_6531_001) ...
Page 117
... International Electrotechnical Commission MPU Microprocessor Unit (CPU) PLL Phase-locked loop RMS Root Mean Square SFR Special Function Register SOC System on Chip SPI Serial Peripheral Interface TOU Time of Use UART Universal Asynchronous Receiver/Transmitter v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 117 ...
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... Real-Time Clock (RTC): observing RTC timing on TMUXOUT pin, corrected values for RTCA_ADJ, and achievable frequency step. 6) 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F (Page 45): Added caution about not sourcing current in or out of DIO pins. Updated Figure 10 : Connecting an External Load to DIO Pins. ...
Page 119
... Removed access to I/O RAM from SPI Port description. 10) Updated numerous parameters in Electrical Specification (tem- perature sensor, supply current for mission and battery modes). 11) Corrected number of pre-boot cycles in Flash Memory Section. 12) Updated entries in I/O RAM table under “Wake” column. Data Sheet 71M6531D/F-71M6532D/F 119 ...
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... Data Sheet 71M6531D/F-71M6532D/F © 2008-2010 Teridian Semiconductor Corporation. All rights Reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Single Converter Technology is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. Intel is a registered trademark of Intel Corporation. ...