DS80C400 Maxim, DS80C400 Datasheet - Page 3

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

Note 3: While the specifications for V
Note 4: Current measured with 75MHz clock source on XTAL1, V
Note 5: While the specifications for V
Note 6: Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
Note 7: This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (V
Note 8: The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
Note 9: Port 3 pins 3.6 (WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition of
Note 10: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to
Note 11: Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port
Note 13: The OW pin (when configured to output a 1) at V
AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: t
Note 4: The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
Note 5: All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following signals,
Note 6: For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid bus
Note 7: References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
External Crystal Frequency
External Clock Oscillator Frequency
ALE Pulse Width
Port 0 Instruction Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instruction In
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
PSEN Low to Address Float
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
CC3
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
= 3.0V to 3.6V, V
most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be
desirable to use a more accurate external reset.
given, there is a guaranteed separation between these two voltages.
disconnected.
given, there will be a guaranteed separation between these two voltages.
interface function (in parentheses) are as follows: Port 3.6-3.7 (WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-6.5
(CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).
pin state can be achieved by applying RST = V
circuit drives the ports hard for two clock cycles. A weak pullup device (V
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
either WR or RD from a 0 to a 1.
1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
maximum at approximately 2V.
0 pin is driven by an external memory source.
CRS, COL, MDIO) at V
CLCL
External Clock Oscillator (XTAL1) Characteristics table.
when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3),
Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
contention.
determing absolute signal timing with respect to the external clock.
, t
CLCH
PARAMETER
, t
CHCL
are time periods associated with the internal system clock and are related to the external clock (t
CC1
IN
= 1.8V ±10%, T
= 3.6V.
PFW3
PFW1
and V
and V
RST3
RST1
overlap, the design of the hardware makes it such that this is not possible. Within the ranges
overlap, the design of the hardware makes it such that this is not possible. Within the ranges
A
SYMBOL
= -40°C to +85°C.)
1 / t
1 / t
CC3.
t
t
t
t
t
t
t
t
t
t
t
PLPH
AVIV0
AVIV2
AVLL
LLAX
PLAZ
LHLL
LLPL
LLIV
PLIV
PXIX
IN
CLK
CLK
= 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
3 of 97
CC3
15.0
21.7
MIN
1.7
4.7
3.7
0
= 3.6V, V
75MHz
MAX
14.3
21.0
27.7
9.7
8.3
0
CC1
OH1
= 2.0V, EA and RST = 0V, Port0 = V
) remains in effect following the strong two-clock cycle
t
CLCL
2t
t
t
t
CHCL
CLCH
CLCH
CLCL
+ t
MIN
DC
16
11
16
11
4
0
VARIABLE CLOCK
CHCL
- 5
- 2
- 3
- 5
- 5
2t
3t
CLCL
CLCL
3t
2t
t
CLCL
CLCL
18.75
18.75
CLCL
MAX
+ t
+ t
37.5
37.5
40
75
0
CLCH
CLCH
- 5
- 19
-17
CLK
) as defined in the
CC3
- 19
- 19
, all other pins
OH2
). This I/O
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns