DS1977 Maxim, DS1977 Datasheet - Page 8

• Manufacturer Part Number: DS1977
• Description: The DS1977 is a 32KB EEPROM in a rugged iButton® enclosure
• Manufacturer: Maxim

passwords, check whether the new password has been successfully installed. See Verify Password command for
details. Once enabled, changing the passwords or disabling password checking requires the knowledge of the
current full-access password.
VERSION REGISTER
The DS1977 includes a read-only Version register, which is not a component of the memory map. Therefore, a
special command is used to read this register. The Chip Revision number enables application software to
automatically use the appropriate software driver in case of different logical behavior.
Version Register Bitmap
Bits 0 to 4 have no function. They always read 0.
Register Details
Figure 6. ADDRESS REGISTERS
ADDRESS REGISTERS AND TRANSFER STATUS
Because of the serial data transfer, the DS1977 employs three address registers, called TA1, TA2, and E/S (Figure
6). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which
data will be sent to the master upon a Read command. Register E/S acts like a byte counter and Transfer Status
register. It is used to verify data integrity with write commands. Therefore, the master only has read access to this
register. The lower six bits of the E/S register indicate the address of the last byte that has been written to the
scratchpad. This address is called Ending Offset. Bit 6 of the E/S register, called PF, is set if the number of data
bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss of
power. A valid write to the scratchpad will clear the PF bit. Note that the lowest six bits of the target address also
determine the address within the scratchpad, where intermediate storage of data will begin. This address is called
byte offset. If the target address for a Write command is 103Ch for example, then the scratchpad will store
incoming data beginning at the byte offset 3Ch and will be full after only four bytes. The corresponding ending
offset in this example is 3Fh. For best economy of speed and efficiency, the target address for writing should point
to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 64-byte capacity of the scratchpad is
available, resulting also in the ending offset of 3Fh. However, it is possible to write one or several contiguous bytes
somewhere within a page. The ending offset together with the Partial Flag support the master checking the data
integrity after a Write command. The highest valued bit of the E/S register, called AA is valid only if the PF flag
reads 0. If PF is 0 and AA is 1, a copy has taken place. The AA bit is cleared when the device receives a write
scratchpad command.
(N/A)
VER: Chip Revision
Indicator
VER2
b7
BIT DESCRIPTION
Target Address (TA1)
Target Address (TA2)
Ending Address with
Data Status (E/S)
VER1
b6
(Read Only)
VER0
b5
b0 to b4
b5 to b7
T15
AA
BIT(S)
T7
b4
0
T14
PF
T6
These bits are all 0.
Chip revision code. The initial version of the DS1977 will have all
revision bits set to 0.
b3
0
T13
E5
T5
b2
0
8 of 29
T12
E4
T4
b1
0
T11
T3
E3
DEFINITION
b0
0
T10
E2
T2
T1
T9
E1
E0
T0
T8
DS1977