DS3231M Maxim, DS3231M Datasheet - Page 17

• Manufacturer Part Number: DS3231M
• Description: The DS3231M is a low-cost, extremely accurate, I²C real-time clock (RTC)
• Manufacturer: Maxim

Bit_ Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold time requirements (see
Figure 1). Data is shifted into the device during the
rising edge of the SCL.
Bit_Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (see Figure 1) before the next rising
edge of SCL during a bit read. The device shifts out
each bit of data on SDA at the falling edge of the
previous SCL pulse and the data bit is valid at the
rising edge of the current SCL pulse. Remember that
the master generates all SCL clock pulses including
when it is reading bits from the slave.
Acknowledge_ (ACK_ and_ NACK): An acknowledge
(ACK) or not acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The
device receiving data (the master during a read or
the slave during a write operation) performs an ACK
by transmitting a 0 during the ninth bit. A device per-
forms a NACK by transmitting a 1 during the ninth bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte_Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgment is read using the bit read
definition.
Byte_Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
Slave_ Address_ Byte: Each slave on the I 2 C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
±5ppm, I
See Figure 9 for an I 2 C communication example.
bits and the R/W bit in the least significant bit. The
device’s slave address is D0h and cannot be modi-
fied by the user. When the R/W bit is 0 (such as in
D0h), the master is indicating it writes data to the
slave. If R/W = 1 (D1h in this case), the master is
indicating it wants to read from the slave. If an incor-
rect slave address is written, the device assumes the
master is communicating with another I 2 C device
and ignore the communication until the next START
condition is sent.
Memory_Address: During an I 2 C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the
slave address byte.
Writing_a_Single_Byte_to_a_Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowl-
edgment during all byte write operations.
Writing_Multiple_Bytes_to_a_Slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple data
bytes, and generates a STOP condition.
Reading_a_Single_Byte_from_a_Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requir-
ing the master to keep track of the memory address
counter is impractical, use the method for manipulat-
ing the address counter for reads.
Manipulating_ the_ Address_ Counter_ for_ Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the mas-
ter generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
2
C Real-Time Clock
I
2
C Communication
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