DS1677 Maxim, DS1677 Datasheet - Page 7

• Manufacturer Part Number: DS1677
• Description: The DS1677 portable system controller is a circuit that incorporates many of the functions necessary for low-power portable products integrated into one chip
• Manufacturer: Maxim

STATUS REGISTER
CU (Conversion Update In Progress). When this bit is a one, an update to the ADC Register (register
0Eh) will occur within 488 μs. When this bit is a zero, an update to the ADC Register will not occur for at
least 244 μs.
LOBAT (Low Battery Flag). This bit reflects the status of the backup power source connected to the
V
LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag). A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up: EOSC , TD0 and TD1. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1677 provides automatic backup and write protection for an external SRAM. This function is
provided by gating the chip enable signal and by providing a constant power supply through the V
The DS1677 nonvolatizes the external SRAM by write protecting the SRAM and by providing a back–up
power supply in the absence of V
prohibited by forcing
the end of t
POWER-FAIL COMPARATOR
The PFI input is connected to an internal reference. If PFI is less than 1.25V,
fail comparator can be used as an undervoltage detector to signal an impending power supply failure.
comparator is turned off and
ADDING HYSTERESIS TO THE POWER-FAIL COMPARATOR
Hysteresis adds a noise margin to the power-fail comparator and prevents
is near the power-fail comparator trip point. Figure 8 shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when V
(V
R2. R3 should be chosen in manner to prevent it from loading down the
noise filtering and has a value of typically 1.0F. See Figure 8 for a schematic diagram and equations.
PFO
BAT
BIT 7
TRIP
CU
can be used as a P interrupt input to prepare for power-down. For battery conservation, the
pin. When V
). Resistors R2 and R3 add hysteresis. R3 will typically be an order of magnitude greater than R1 or
RPU
.
LOBAT
BIT 6
BAT
CE0
is greater than 2.5V, LOBAT is set to a logic 0. When V
high regardless of the level of
PFO
BIT 5
0
is held low when in battery-backed mode
CC
. When V
BIT 4
0
CC
7 of 18
falls below V
BIT 3
CEI
0
. Upon power-up, access is prohibited until
PF
, access to the external SRAM is
BIT 2
0
PFO
IN
PFO
falls to the desired trip point
PFO
from oscillating when V
pin. Capacitor C1 adds
BIT 1
BAT
goes low. The power-
0
is less than 2.3V,
BIT 0
IRQF
CCO
pin.
IN