DS1557 Maxim, DS1557 Datasheet - Page 9

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DS1557

Manufacturer Part Number
DS1557
Description
The DS1557 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) with an RTC alarm, watchdog timer, power-on reset, battery monitor, and 512k x 8 nonvolatile static RAM
Manufacturer
Maxim
Datasheet

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DS1557 4Meg, Nonvolatile, Y2K-Compliant Timekeeping RAM
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of timeout into the 8-bit Watchdog Register (Address 7FFF7h). The
five Watchdog Register bits BMB4 to BMB0 store a binary multiplier and the two lower order bits RB1
to RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The
watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2-
bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 X 1 second or
3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF)
is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read
or the Watchdog Register (7FFF7h) is read or written.
The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,
the watchdog will activate the
/FT output when the watchdog times out.
IRQ
When WDS is set to a 1, the watchdog will output a negative pulse on the
output for a duration of
RST
40 ms to 200 ms. The Watchdog Register (7FFF7h) and the FT bit will reset to a 0 at the end of a
watchdog timeout when the WDS bit is set to a 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The
timeout period then starts over. Writing a value of 00h to the Watchdog Register disables the watchdog
timer. The watchdog function is automatically disabled upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to the IRQ/FT output and the frequency test function is
activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to a 0:
WDS = 0, BMB0 to BMB4 = 0, RB0 to RB1 = 0, AE = 0, ABE = 0.
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