DS1391 Maxim, DS1391 Datasheet - Page 14

• Manufacturer Part Number: DS1391
• Description: The low-voltage serial-peripheral interface (SPI™) DS1390/DS1391/DS1394 and the low-voltage 3-wire DS1392/DS1393 real-time clocks (RTCs) are clocks/calendars that provide hundredths of a second, seconds, minutes, hours, day, date, month, and ye
• Manufacturer: Maxim

Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
Table 3 shows the address map for the DS1390–
DS1393 RTC and RAM registers. The RTC registers are
located in address locations 00h to 0Fh in read mode,
and 80h to 8Fh in write mode. During a multibyte
access, when the address pointer reaches 0Fh, it
wraps around to location 00h. On the falling edge of the
CS pin (DS1390/DS1391/DS1394) or the rising edge of
CE (DS1392/DS1393), the current time is transferred to
a second set of registers. The time information is read
from these secondary registers, while the clock may
continue to run. This eliminates the need to re-read the
registers if the main registers update during a read. To
avoid rollover issues when writing to the time and date
registers, all registers should be written before the hun-
dredths-of-seconds registers reaches 99 (BCD).
When reading from the hundredths of seconds register,
there is a possibility that the data transfer happens at the
same time as an increment of the register. If this occurs,
the data in the buffer may be incorrect. The chances of
this happening is approximately 170ppb. There are two
ways to deal with this.
Table 3. Address Map
14
ADDRESS
WRITE
8Ah
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
____________________________________________________________________
ADDRESS
READ
0Ah
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Century
BIT 7
AM1
AM2
0
0
0
0
0
Tenths of Seconds
Tenths of Seconds
12/24
BIT 6
0
0
0
Address Map
10 Year
10 Seconds
10 Seconds
10 Minutes
10 Minutes
10 Hour
AM/PM
BIT 5
0
0
10 Date
Month
BIT 4
Hour
10
10
0
BIT 3
0
The first method is to synchronize enabling the device
(CE or CS) with the square wave or interrupt output
(DS1390–DS1394). Enabling the device, either after
detecting the falling edge of the interrupt output or the
rising edge of the square-wave output, ensures that the
two events are not simultaneous.
The second method is to read the hundredths of sec-
onds register until the data for two consecutive reads
match. With this method, the master must be able to
read the register at least twice within the 10ms update
period of the hundredths of seconds register.
Either of the described methods ensures that the data in
all the registers is correct. If the hundredths of seconds
register is not used, it is also possible for the same prob-
lem to occur when reading the seconds register. The
probability of an error is inversely proportional to the rate
of the register's update frequency in relation to the hun-
dredth of seconds register, so the error rate for the sec-
onds register would be approximately 1.7ppb. The same
methods used for the hundredth of seconds register
would be used for the seconds register.
Hundredths of Seconds
Hundredths of Seconds
BIT 2
Seconds
Seconds
Minutes
Minutes
Month
Hour
Date
Year
BIT 1
Day
BIT 0
Hundredths
Hundredths
of Seconds
of Seconds
FUNCTION
Seconds
Minutes
Century
Month/
Hours
Alarm
Alarm
Alarm
Date
Year
Day
1–12 +AM/PM
Century BCD
00–59 BCD
00–59 BCD
01–31 BCD
00–99 BCD
00–59 BCD
00–59 BCD
00–23 BCD
0–99 BCD
0–99 BCD
1–7 BCD
01–12 +
RANGE