DS1251 Maxim, DS1251 Datasheet - Page 4

• Manufacturer Part Number: DS1251
• Description: The DS1251 4096K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 512K words by 8 bits) with a built-in real-time clock
• Manufacturer: Maxim

be kept valid throughout the write cycle.
(t
write cycles to avoid bus contention. However, if the output bus has been enabled (
then
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point, V
operation and SRAM data are maintained from the battery until V
The 3.3V device is fully accessible and data can be written or read only when V
When V
the device power is switched from V
greater than V
below V
nominal levels.
All control, data, and address signals must be powered down when V
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the
the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
CE
CE
WR
and
and
) before another cycle can be initiated. The
WE
SO
CC
BAT
OE
will disable the outputs in t
WE
(battery supply level), device power is switched from the V
falls below the power-fail point, V
. RTC operation and SRAM data are maintained from the battery until V
control of the phantom clock starts the pattern recognition sequence by moving a pointer to
BAT
control of the SmartWatch. These 64 write cycles are used only to gain access to the
, the device power is switched from V
CC
is below the power-fail point, V
ODW
CC
to the backup supply (V
from its falling edge.
WE
PF
must return to the high state for a minimum recovery time
, access to the device is inhibited. If V
OE
4 of 20
control signal should be kept inactive (high) during
PF
CC
(point at which write protection occurs), the
to the backup supply (V
BAT
CC
is returned to nominal levels.
) when V
CC
is powered down.
CC
CC
pin to the backup battery. RTC
falls below the battery switch
CC
drops below V
CC
CC
BAT
is greater than V
CE
is greater than V
PF
) when V
is less than V
CC
and
is returned to
PF
OE
. If V
CC
active)
drops
PF
BAT,
PF
PF.
is
.