DS1244 Maxim, DS1244 Datasheet - Page 4

• Manufacturer Part Number: DS1244
• Description: The DS1244 256k NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM) (organized as 32k words by 8 bits) with a built-in real-time clock
• Manufacturer: Maxim

DS1244/DS1244P
DESCRIPTION
The DS1244 256K NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32K words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors V
for an out-of-tolerance
CC
condition. When such a condition occurs, the lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.
The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
PACKAGES
The DS1244 is available in two packages: 28-pin encapsulated DIP and 34-pin PowerCap module. The
28-pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The
34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on
top of the DS1244P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap
is DS9034PCX.
RAM READ MODE
The DS1244 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within t
ACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t
for
CO
CE or t
for OE , rather than address access.
OE
RAM WRITE MODE
The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (t
) before another cycle can be initiated. The OE control signal should be kept inactive (high)
WR
during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE
active) then WE will disable the outputs in t
from its falling edge.
ODW
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