DS28E04-100 Maxim, DS28E04-100 Datasheet - Page 10

• Manufacturer Part Number: DS28E04-100
• Description: The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs
• Manufacturer: Maxim

PIO Activity Latch State Register
The data in this register represents the current state of the PIO activity latches. This register is read using the Read
Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 0. A state transition on a PIO pin, HighLow or
LowHigh, of a duration greater than t
is cleared to 00h by a power-on reset, or by successful execution of the Reset Activity Latches command.
The next three registers control the device's participation a Conditional Search ROM sequence. The interaction of
the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7.
There is a selection mask, SM, to select the participating PIOs, a polarity selection SP to specify for each channel
whether the channel signal needs to be 1 or 0 to qualify, and a PLS bit to select either the activity latches or PIO
pins as inputs. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally
selects the ANDed or ORed result as the conditional search response signal CSR. If CT is 0, the channel signal of
at least one of the selected channels must match the corresponding polarity. If CT is 1, the channel signals of all
selected channels must match the corresponding polarity.
Figure 7. CONDITIONAL SEARCH LOGIC
Conditional Search Channel Selection Mask Register
The data in this register controls whether a PIO channel qualifies for participation in the conditional search
command. To include a PIO channel, the bits in this register that correspond to those channels need to be set to 1.
This register can only be written through the Write Register command. This register is read/write. Each bit is
associated with the respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0
and cannot be changed to 1. This register is cleared to 00h by a power-on reset.
ADDR
ADDR
0222h
0223h
AL0
P0
AL1
P1
b7
b7
0
0
PLS
Channel 0
Channel 1
b6
b6
0
0
b5
b5
0
0
SP0
SP1
PWMIN
b4
b4
0
0
causes the associated bit in the register to be set to a 1. This register
10 of 37
b3
b3
0
0
SM0
SM1
b2
b2
0
0
SM1
AL1
b1
b1
SM0
AL0
b0
b0
CT
PORL
CSR