DS28CM00 Maxim, DS28CM00 Datasheet
DS28CM00
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DS28CM00 Summary of contents
Page 1
... I²C and SMBus interface. The registration number is a factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit family code (70h). In SMBus mode, the DS28CM00 resets its communication interface if it detects a bus fault condition. APPLICATIONS ...
Page 2
... HD:STA ≥ 2. ≥ 2. LOW CC V < 2. (Note 8) HIGH t (Note 8) SU:STA DS28CM00: I²C/SMBus Silicon Serial Number -40°C to +85°C -55°C to +125°C See IPC/JEDEC J-STD-020 (-40°C to +85°C, see Note 1) MIN TYP MAX 1.62 5. 200 0.3 × -0 0.25 × -0.3 ...
Page 3
... The DS28CM00 does not obstruct the SDA and SCL lines if V Note 7: The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL stays at the same logic level or SDA stays low for this interval, the DS28CM00 behaves as though it has sensed a STOP condition. System Requirement ...
Page 4
... SRAM Unique Registration Number Each DS28CM00 has a unique Registration Number that is 64 bits long. The registration number begins with the family code at address 00h followed by the 48-bit serial number (LS-byte at the lower address) and ends at address 07h with the CRC (Cyclic Redundancy Check) of the first 56 bits. This CRC is generated using the ...
Page 5
... To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. The slave address to which the DS28CM00 responds is shown in Figure 3. The slave address is part of the slave-address/direction byte. The last bit of the slave-address/direction byte (R/W) defines the data direction. ...
Page 6
... SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH period of the acknowledge-related clock pulse plus the required setup and hold time (t SCL and t before the rising edge of SCL). SU:DAT DS28CM00: I²C/SMBus Silicon Serial Number R/ W ACK bit Acknowledgment ...
Page 7
... When the end of the memory is reached (address 08h), the address pointer wraps around to 00h. To read from an arbitrary address, the master must first access the DS28CM00 in write access mode and specify a new memory address. The address pointer remains unchanged if the device resets its communication interface due to a bus timeout in SMBus mode ...
Page 8
... P According to the I²C specification, a slave device must be able to sink at least 3mA specification requires a current sink capability of 4mA at 0.4V. The DS28CM00 can sink at least 4mA at 0.4V V over its entire operating voltage range. This DC characteristic determines the minimum value of the pullup resistor: Rpmin = ( ...
Page 9
... SCL SDA SCL DS28CM00 is calculated as " line. P "Minimum Rp" Max. Load at Min. Rp fast mode 2.5 3 3.5 Pull-up Voltage DS28CM00: I²C/SMBus Silicon Serial Number To additional devices V CC GND = 300ns/(C *ln(7/3)). For a bus PMAX B " line) and then calculating P 600 500 400 300 ...