DS2408 Maxim, DS2408 Datasheet - Page 4

• Manufacturer Part Number: DS2408
• Description: The DS2408 is an 8-channel, programmable I/O 1-Wire® chip
• Manufacturer: Maxim

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: The earliest recognition of a negative edge is possible at t
Note 12: Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
Note 13: Interval during the negative edge on I/O at the beginning of a presence detect pulse between
Note 14: ε in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
Note 15: δ in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
Note 16: Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
Note 17: Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
Note 18: Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
System Requirement
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
If a 2.2kΩ resistor is used to pull up the data line to V
the parasite capacitance does not affect normal communications.
Guaranteed by design—not production tested.
V
function of V
are valid at V
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to V
low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After V
detected as logic '0'.
before.
comparison table below.
the time at which the voltage is 90% of V
V
up from V
t
up from V
the master to pull the line low is t
the time at which the voltage is 90% of V
V
(for the RSTZ pin). For a pulse duration t
t
pulse will be recognized and latched.
No requirement for current balance among different pins.
W1LMAX
PWMIN(min)
TL
PUP
PUP
and V
.
. PIO pullup resistor = 2.2kΩ.
TH
+ t
TH
IL
IL
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
< t
F
to V
to the input high threshold of the bus master. The actual maximum duration for
- ε and t
are functions of the internal supply voltage, which in parasitic power mode, is a
PUP
PUP
PW
< t
TH
and the 1-Wire recovery times. The V
= 5.25V. In any case, V
. The actual maximum duration for the master to pull the line low is
PWMIN(max)
W0LMAX
+ t
, the pulse may or may not be rejected. If t
F
- ε respectively.
RLMAX
4 of 39
+ t
TL
PW
PUP
PUP
F
< V
.
: If t
and the time at which the voltage is 10% of
and the time at which the voltage is 10% of
TH
PW
ILMAX
< V
< t
PUP
PUP
PWMIN(min)
TH
whenever the master drives the line
, 5µs after power has been applied,
.
REH
and V
after V
, the pulse will be rejected. If
TL
maximum specifications
TH
has been reached
PW
> t
PWMIN(max)
HY
to be
the
DS2408